Kaushik Vaidyanathan

Building trusted ICs using split fabrication

Due to escalating manufacturing costs the latest and most advanced semiconductor technologies are often available at off-shore foundries. Utilizing these facilities significantly limits the trustworthiness of the corresponding integrated circuits for mission critical applications. We address this challenge of cost-effective and trustworthy CMOS manufacturing for advanced technologies using split fabrication. Split fabrication, the process of splitting an IC into an untrusted and trusted component, enables the designer to exploit the most advanced semiconductor manufacturing capabilities available offshore without disclosing critical IP or system design intent. We show that split fabrication after the Metal1 layer is secure and has negligible performance and area overhead compared to complete IC manufacturing in the off-shore foundry. Measurements from split fabricated 130nm testchips demonstrate the feasibility and efficacy of the proposed approach.

Efficient and secure intellectual property (IP) design with split fabrication

Split fabrication, the process of splitting an IC into an untrusted and trusted tier, facilitates access to the most advanced semiconductor manufacturing capabilities available in the world without requiring disclosure of design intent. While researchers have investigated the security of logic blocks in the context of split fabrication, the security of IP blocks, another key component of an SoC, has not been examined. Our security analysis of IP block designs, specifically embedded memory and analog components, shows that they are vulnerable to “recognition attacks” at the untrusted foundry due to the use of standardized floorplans and leaf cell layouts. We propose methodologies to design these blocks efficiently and securely, and demonstrate their effectiveness using 130nm split fabricated testchips.

Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node

The 14 nm node is seeing the dominant use of three-dimensional FinFET architectures, local interconnects, multiple patterning processes and restricted design rules. With the adoption of these new process technologies and design styles, it becomes necessary to rethink the standard cell library design methodologies that proved successful in the past. In this paper, we compare the design efficiency and manufacturability of standard cell libraries that use either unidirectional or bidirectional Metal 1. In contrast to previous nodes, a 14 nm 9-track unidirectional standard cell layout results in up to 20% lower energy-delay-area product as compared to the 9-track bidirectional standard cell layout. Manufacturability assessment shows that the unidirectional standard cell layouts save one exposure on Metal 1, reduces process variability by 10% and layout construct count by 2-3X. As a result, the unidirectional standard cell layout could serve as a key enabler for affordable scaling.

Design Automation Framework for Application-Specific Logic-in-Memory Blocks

This paper presents a design methodology forhardware synthesis of application-specific logic-in-memory(LiM) blocks. Logic-in-memory designs tightly integrate specializedcomputation logic with embedded memory, enablingmore localized computation, thus save energy consumption. Asa demonstration, we present an end-to-end design frameworkto automatically synthesize an interpolation based logic-in-memoryblock named interpolation memory, which combinesa seed table with simple arithmetic logic to efficiently evaluatefunctions. In order to support multiple consecutive seed dataaccess that is required in the interpolation operation, wesynthesize the physical memory into the novel rectangular accesssmart memory blocks. We evaluated a large designspace of interpolation memories in sub-20 nm commercialCMOS technology by using the proposed design framework.Furthermore, we implemented a logic-in-memory based computedtomography (CT) medical image reconstruction systemand our experimental results show that the logic-in-memorycomputing method achieves orders of magnitude of energysaving compared with the traditional in-processor computing.

Enabling application-specific integrated circuits on limited pattern constructs

Implementing sub-22nm designs using a limited set of pattern constructs can eliminate hotspot risk and can control systematic variability. Pattern regularity can incur a cell-level density penalty that is minimized or eliminated by co-optimization with circuits. More importantly, design with a limited set of pattern constructs can remove the limitations imposed by complex design rules, thus facilitating flexible synthesis of logic and memory blocks in place of hard IP.

Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack

Split fabrication, the process of splitting an IC into an untrusted and trusted tier, facilitates access to the most advanced semiconductor manufacturing capabilities available in the world without requiring disclosure of design intent. While obfuscation techniques have been proposed to prevent malicious circuit insertion or modifications in the untrusted tier, detecting a pernicious reliability attack induced in the offshore foundry is more elusive. We describe a methodology for exhaustive testing of components in the untrusted tier using a specialized test-only metal stack for selected sacrificial dies.

Design implications of extremely restricted patterning

Abstract. Escalating manufacturing cost and complexity is challenging the premise of affordable scaling. With lithography accounting for a large fraction of wafer costs, researchers are actively exploring several cost-effective alternative lithographic techniques, such as directed self-assembly, self-aligned multiple patterning, etc. However, most of the alternative lithographic techniques are restrictive, and it is important to understand the impact of such pattering restrictions on system-on-chip (SoC) design. To this end, we artificially restricted all layers in a 14 nm process to be pure gratings and observed that the pure gratings approach results in an inefficient SoC design with several process integration concerns. To come up with a technology definition that is mindful of designer requirements, it is essential to undertake a holistic design technology co-optimization (DTCO) considering several SoC design elements, such as standard cell logic, static random access memory bitcells, analog blocks, and physical synthesis. Our DTCO on the IBM 14 nm process with additional 10- and 7-nm node-like pattern restrictions leads us to converge on a set of critical pattern constructs that are required for an efficient and affordable SoC design.

Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip

Abstract. For the past four decades, cost and features have driven complementary metal-oxide semiconductor (CMOS) scaling. Severe lithography and material limitations seen below the 20-nm node, however, are challenging the fundamental premise of affordable CMOS scaling. Just continuing to co-optimize leaf cell circuit and layout designs with process technology does not enable us to exploit the challenges of sub-20-nm CMOS. For affordable scaling, it is imperative to work past sub-20-nm technology impediments while exploiting its features. To this end, we propose to broaden the scope of design technology co-optimization (DTCO) to be more holistic by including microarchitecture design and computer-aided design, along with circuits, layout, and process technology. Furthermore, we undertook such a holistic DTCO for all critical design elements such as embedded memory, standard cell logic, analog components, and physical synthesis in a 14-nm process. Measurements results from experimental designs in a representative 14-nm process from IBM demonstrate the efficacy of the proposed approach.

Local loops for robust inter-layer routing at sub-20 nm nodes

As the metal pitch continues to shrink, it becomes inefficient, if not impossible, to use traditional via redundancy schemes at and below the 14 nm node. Double-cut vias and via bar connections will either block many adjacent routing resources or make it impossible to pattern at these advanced technologies nodes. In this paper we examine a scalable via redundancy strategy based on local loops. We evaluate the yield and timing impact of local loops and use a 14 nm standard cell library and functional block designs to assess the design cost of local loops. Furthermore, lithography contours and process window simulations are used to demonstrate the manufacturability of this structure. With supporting EDA tools and design-technology co-optimization (DTCO), local loops will become an important via redundancy topology at sub-20nm nodes.

Rethinking ASIC design with next generation lithography and process integration

Given the deployment delays for EUV, several next generation lithography (NGL) options are being actively researched. Several cost-effective NGL solutions, such as self-aligned double patterning through sidewall image transfer (SIT) and directed self-assembly (DSA), in conjunction with process integration challenges, mandate grating-like pattern design. As part of the GRATEdd project, we have evaluated the design cost of grating-based design for ASICs (application specific ICs). Based on our observations we have engineered fundamental changes to the primary ASIC design components to make scaling affordable and useful in deeply scaled sub-20 nm technologies: unidirectional-M1 based standard cells, application-specific smart SRAM synthesis, and statistical and self-healing analog design.