Neal Lafferty

Directed self-assembly graphoepitaxy template generation with immersion lithography

Abstract. We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

Lithography yield enhancement through optical rule checking

Use of simulation-based printing verification prior to mask tapeout has become standard practice for mask layers printed with low-k1 lithography processes. At 90nm and above, this methodology has proven beneficial and sufficient for guaranteeing a usable mask. However, it is anticipated that at 65nm and below, a simulation at a single point within the process window may fail to capture all important marginal areas of a mask prior to tapeout. Modern lithography simulation tools are proven capable of accurately predicting printing behavior through process window. Unfortunately, due to long run times, use of such tools is restricted to small simulation areas. Recent developments in vectorial thin-film OPC models have enabled full process window prediction on large product die. Although such models are extremely fast compared to conventional lithography simulation tools, the prospect of simulating a full chip at multiple dose and focus points is quite daunting. In an effort to reduce the expected longer run times when simulating full chips at multiple focus and dose conditions, we have developed two flows which reduce the total run time enormously. These so-called pre-targeting flows are explained, and the limitations and future prospects of the flows are described.

Directed self-assembly (DSA) grapho-epitaxy template generation with immersion lithography

In this paper, we present an optimization methodology for the template designs of sub-resolution contacts using directed self-assembly (DSA) with grapho-epitaxy and immersion lithography. We demonstrate the flow using a 60nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of Template Error Enhancement Factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity, and evaluate optimized template designs with TEEF metrics. Our data shows that SMO is critical to achieve sub-80nm non- L0 pitches for DSA patterns using 193i.

Practical DTCO through design/patterning exploration

Design Technology Co-Optimization (DTCO) becomes more important with every new technology node. Complex patterning issues can no longer wait to be detected experimentally using test sites because of compressed technology development schedules. Simulation must be used to discover complex interactions between an iteration of the design rules, and a simultaneous iteration of an intended patterning technology. The problem is often further complicated by an incomplete definition of the patterning space. The DTCO process must be efficient and thoroughly interrogate the legal design space for a technology to be successful. In this paper we present our view of DTCO, called Design and Patterning Exploration. Three emphasis areas are identified and explained with examples: Technology Definition, Technology Learning, and Technology Refinement. The Design and Patterning Exploration flows are applied to a logic 1.3x metal routing layer. Using these flows, yield limiting patterns are identified faster using random layout generation, and can be ruled out or tracked using a database of problem patterns. At the same time, a pattern no longer in the set of rules should not be considered during OPC tuning. The OPC recipe may then be adjusted for better performance on the legal set of pattern constructs. The entire system is dynamic, and users must be able to access related teams output for faster more accurate understanding of design and patterning interactions. In the discussed example, the design rules and OPC recipe are tuned at the same time, leading to faster design rule revisions, as well as improved patterning through more customized OPC and RET.

Full-flow RET creation, comparison, and selection

Patterning scaling trends are expected to continue until at least the 5 nm node. With the introduction of EUV now delayed until at least the 7 nm node, 193i patterning will continue mainstream use for the foreseeable future. This scaling increases reliance on optimized OPC and illumination and imposes strict requirements on RET solutions, which we define here as source, optics, and mask synthesis (including SRAF). Along with the patterning requirements, any solution must be calculated efficiently. To meet these requirements, a new RET Selection flow has been built using the Calibre platform. This flow includes SMO, Mask synthesis to further tune the output mask, Verification, and Analysis. The entire flow is session based, allowing runs to be cloned, queued, and compared. The flow is built on a robust GUI framework featuring persistent database integration. The central component of the flow is a new SMO algorithm that offers improved scalability using parallel implementation, and improved accuracy using thick mask modeling and resist models. Lithography-aware mask manufacturability limit enforcement is possible using an integrated inverse lithography tool. This also allows large area patterns to be included for RET benchmarking purposes. Finally, the analysis and visualization stages of the flow allow a particular solution to be compared against other candidates using any image metric desired. Comparison metrics can be customized for layer and customer requirements. In this paper, we will summarize the key points of our flow, and demonstrate it using several experiments.

Enabling enhanced EUV lithographic performance using advanced SMO, OPC, and RET (Conference Presentation)

The current industry standard tantalum-based mask absorber (60 nm TaBN) gives strong 3D electromagnetic field (EMF) effects at wafer level, such as shadowing and pitch-dependent best focus shifts. A thinner mask absorber with higher EUV extinction coefficient or a phase shifting mask can mitigate 3D EMF effects [1]. The alternative mask absorber materials would enable further downscaling to foundry 5nm node using state-of-the-art EUV scanners (with 0.33 numerical aperture “NA”) and facilitate future high NA imaging using single exposure. Here we evaluate insertion options on the patterning roadmap for alternative EUV mask absorbers, including high-k absorbers and attenuated phase shifting masks (attPSM) [1-2]. All studies are using relevant designs from foundry N5 logic node. Two alternative mask candidates are compared with the standard TaBN mask. We bring theoretical proof of concept that alternative mask absorber materials generate significant imaging gain in terms of established success criteria. On a set of predefined types of clips (with variations of 1D/2D, horizontal/vertical, dense/isolated patterns), we seek for higher depth of focus (DoF), higher image log slope (ILS), high illumination efficiency (ideally it would be equal to 1), lower pattern shift through focus (i.e., lower tele-centricity errors), lower mask error enhancement factor (MEEF). Source mask optimization (SMO) on N5 logic clip shows a more balanced source and larger common process window for high-k absorber over Ta-based absorber. Using the optical proximity correction (OPC) engine with high-k mask absorber, shows significant gain on overlapping process window (PW), process variation (PV) band, and less line end shortening. Applying advanced Resolution Enhancement Techniques (RET), sub-resolution assist features (SRAFs) on N5 designs demonstrated an improved process in terms of common depth of focus (cDoF), and image shift through focus. It was also observed that the process not using SRAFs with the high-k absorber had superior process window and image shift compared to the Ta-based case with SRAFs. Therefore, adoption of such high-k absorbers could potentially postpone the need for SRAFs.

Ultimate patterning limits for EUV at 5nm node and beyond

The 5nm technology node introduces more aggressive geometries than previous nodes. In this paper, we are introducing a comprehensive study to examine the pattering limits of EUV at 0.33NA. The study is divided into two main approaches: (A) Exploring pattering limits of Single Exposure EUV Cut/Block mask in Self-Aligned-Multi-Patterning (SAMP) process, and (B) Exploring the pattering limits of a Single Exposure EUV printing of metal Layers. The printability of the resulted OPC masks is checked through a model based manufacturing flow for the two pattering approaches. The final manufactured patterns are quantified by Edge Placement Error (EPE), Process Variation Band (PVBand), soft/hard bridging and pinching, Image Log Slope (ILS) and Common Depth of Focus (CDOF)

Impact of aberrations in EUV lithography: metal to via edge placement control

In previous work, we have described how EUV scanner aberrations can be adequately simulated and corrected in OPC across the slit to deliver excellent edge placement control. The problem is that the level of aberration variability from tool to tool is currently quite significant and leads to uncorrectable edge placement errors if OPC is done using one tool while exposure happens on a different tool. In this study, we examine the impact of such edge placement errors for single patterning EUV exposure of metal and via layers with variable aberrations in projection lens systems. Two-layer combined CD and overlay edge placement hotspots can be compounded by aberrations which impact CDs and image shifts, and do so differently depending upon design pattern and pupil fill. Aberration values from current 3300 / 3350 EUV scanners are used and compared to hypothetical ideal tool with no aberrations and demonstrate very significant uncorrectable edge placement errors with current aberrations levels. The net result is a significant reduction in the metal-via combined CD-overlay process window.

Exploring EUV and SAQP pattering schemes at 5nm technology node

For years, Moore’s law keeps driving the semiconductors industry towards smaller dimensions and higher density chips with more devices. Earlier, the correlation between exposure source’s wave length and the smallest resolvable dimension, mandated the usage of Deep Ultra-Violent (DUV) optical lithography system which has been used for decades to sustain Moore’s law, especially when immersion lithography was introduced with 193nm ArF laser sources. As dimensions of devices get smaller beyond Deep Ultra-Violent (DUV) optical resolution limits, the need for Extremely Ultra-Violent (EUV) optical lithography systems was a must. However, EUV systems were still under development at that time for the mass-production in semiconductors industry. Theretofore, Multi-Patterning (MP) technologies was introduced to swirl about DUV optical lithography limitations in advanced nodes beyond minimum dimension (CD) of 20nm. MP can be classified into two main categories; the first one is to split the target itself across multiple masks that give the original target patterns when they are printed. This category includes Double, Triple and Quadruple patterning (DP, TP, and QP). The second category is the Self-Aligned Patterning (SAP) where the target is divided into Mandrel patterns and non-Mandrel patterns. The Mandrel patterns get printed first, then a self-aligned sidewalls are grown around these printed patterns drawing the other non-Mandrel targets, afterword, a cut mask(s) is used to define target’s line-ends. This approach contains Self-Aligned-Double Pattering (SADP) and Self-Aligned- Quadruple-Pattering (SAQP). DUV and MP along together paved the way for the industry down to 7nm. However, with the start of development at the 5nm node and the readiness of EUV, the differentiation question is aroused again, which pattering approach should be selected, direct printing using EUV or DUV with MP, or a hybrid flow that contains both DUV-MP and EUV. In this work we are comparing two potential pattering techniques for Back End Of Line (BEOL) metal layers in the 5nm technology node, the first technique is Single Exposure EUV (SE-EUV) with a Direct Patterning EUV lithography process, and the second one is Self-Aligned Quadruple Patterning (SAQP) with a hybrid lithography processes, where the drawn metal target layer is decomposed into a Mandrel mask and Blocks/Cut mask, Mandrel mask is printed using DUV 193i lithography process, while Block/Cut Mask is printed using SE-EUV lithography process. The pros and cons of each technique are quantified based on Edge-Placement-Error (EPE) and Process Variation Band (PVBand) measured at 1D and 2D edges. The layout used in this comparison is a candidate layout for Foundries 5nm process node.

Enhanced OPC recipe coverage and early hotspot detection through automated layout generation and analysis

State-of-the-art OPC recipes for production semiconductor manufacturing are fine-tuned, often artfully crafted parameter sets are designed to achieve design fidelity and maximum process window across the enormous variety of patterns in a given design level. In the typical technology lifecycle, the process for creating a recipe is iterative. In the initial stages, very little to no “real” design content is available for testing. Therefore, an engineer may start with the recipe from a previous node; adjust it based on known ground rules and a few test patterns and/or scaled designs, and then refine it based on hardware results. As the technology matures, more design content becomes available to refine the recipe, but it becomes more difficult to make major changes without significantly impacting the overall technology scope and schedule. The dearth of early design information is a major risk factor: unforeseen patterning difficulties (e.g. due to holes in design rules) are costly when caught late. To mitigate this risk, we propose an automated flow that is capable of producing large-scale realistic design content, and then optimizing the OPC recipe parameters to maximize the process window for this layout. The flow was tested with a triple-patterned 10nm node 1X metal level. First, design-rule clean layouts were produced with a tool called Layout Schema Generator (LSG). Next, the OPC recipe was optimized on these layouts, with a resulting reduction in the number of hotspots. For experimental validation, the layouts were placed on a test mask, and the predicted hotspots were compared with hardware data.