Kaveh Shakeri

Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI)

The supply voltage decrease and power density increase of future GSI chips demand accurate models for the IR-drop. Compact physical IR-drop models of on-chip power/ground distribution networks are derived for two generic types of packages. In the early stages of design, these models enable accurate estimates of all required power/ground grid interconnect dimensions and chip pad counts that are needed for power distribution. The models also quantify the tradeoff between on-chip interconnect dimensions and the number of I/O pads required for power distribution and therefore enable rigorous chip/package co-design. Comparison with SPICE simulations show less than 1% and 5% error for the wire-bond package and the flip-chip package, respectively.

Compact Physical Models for Power Supply Noise and Chip/Package Co-Design of Gigascale Integration

Compact physical models are derived for predicting power supply noise of chips in the gigascale integration (GSI) era. These models consider both IR-drop and simultaneous switching noise (SSN) and give a quick full waveform description of the first droop power supply noise as well as its peak value. The derivation of these models proceeds by considering a frequency domain representation of power grids and later obtaining time domain equivalents. The derived models enable chip/package co-design in current and future technology nodes by allowing a designer to make tradeoffs in various chip and package parameters such as on-chip wire area, number and sizes of power/ground I/O pads and amount of decoupling capacitance. SPICE simulations show that the worst case peak noise model has less than 4% error.

Temperature variable supply voltage for power reduction

The scaling trend of MOSFETs requires the supply and the threshold voltages to be reduced in future generations. Although the supply voltage is reduced, the total power dissipation and the static power of the chip are increased. Power dissipation is one of the limiting factors in achieving the highest performance of a chip. Therefore, new power reduction techniques are required. In this paper a new technique is introduced to reduce the power consumption. In this technique the supply voltage is changed dynamically as temperature changes. Using this technique, for 70 nm devices the total power consumption of the chip can be reduced by 24% and the static power can be reduced by 40%. This reduction is achieved without any change in the worst-case delay.

Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots

An analytical physical model is derived for the first time to predict the first droop power supply noise for non-uniform current switching conditions and arbitrary functional block sizes. The model not only captures the impact of package parameters and the distributed nature of power grid and decoupling capacitance but also addresses the non-uniformity problem for the power density distribution brought by hot spots. A case study shows that both the frequency domain power noise model and the projected peak noise value have less than 1% error comparing with SPICE simulation.

A compact delay model for series-connected MOSFETs

A compact delay model for series connected MOSFETs has been derived. This model enables accurate prediction of worst-case delay of different logic families such as dynamic logic. It also provides insight into delay change as the device parameters change. Key results show that the relative delay of series connected MOSFETs is almost invariant for different generations of technology.

Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution

An ultralow inductance I/O interconnect, called a coaxial polymer pillar (CoPP) is introduced that is compatible with sea of polymer pillars (SoPP) recently presented. Polymer pillars are highly process-integrated and mechanically flexible (compliant) electrical-optical I/O interconnections that mitigate thermomechanical expansion mismatches. The 100x smaller parasitic inductance of the CoPP (in the range of 0.1 pH) compared to the inductance of a solder bump or a regular polymer pillar makes it an excellent I/O interconnect technology for power distribution. The density of CoPPs may exceed 10/sup 5//cm/sup 2/.

Relative inductance extraction method

A new relative inductance extraction method is defined to solve massive coupled RLC interconnects. The new relative inductance generates a sparse inductance matrix. Therefore, it enables modeling of large circuits with reasonable speed and accuracy. It maintains accuracy for all frequencies, even for the cases that there are no near return paths. Simulations done for a 16 bit bus with each line divided into 16 segments show that this method is 4 times faster than using the dense inductance matrix.

Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method

A new inductance extraction method is defined to accelerate modeling of massively coupled resistance-inductance-capacitance (RLC) interconnects. The new relative inductance generates a sparse inductance matrix. Therefore, it enables modeling of large circuits with reasonable speed and accuracy. It maintains accuracy for a wide frequency range, even for the cases that there are far inductance couplings. It is demonstrated that the relative inductance matrix is equivalent to the conventional partial inductance matrix. Simulations done for a 16-bit bus with each bus line divided into 32 segments show that the simulations using the relative inductance method is 20 times faster and requires 9.5 times less memory compared to the established partial inductance method.

A compact substrate spreading resistance model for SoC

Mixed signal SoC ICs are increasingly being used in commercial products. However, the analog circuits are sensitive to noise which is produced by the digital circuits and propagated by the substrate. In this paper, compact physical 2D and 3D models have been derived for the spreading resistance between multiple contacts within two different substrates. These models can be used to estimate substrate noise.