Masaki Kitsunezuka

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a two-step structure with an inverter- and a Vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of , where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of at a 1-MHz offset frequency. The chip core occupies 0.37 and the measured power consumption is 8.1 mA from a 1.2-V power supply.

A 30-MHz–2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems

A 30-MHz-2.4-GHz complementary metal oxide semiconductor (CMOS) receiver with an integrated tunable RF filter and a dynamic-range-scalable energy detector for both white-space and interference-level sensing in cognitive radio systems is reported. The second-order RF filter has only two stacked transistors, and its use, in combination with a subsequent harmonic rejection mixer, results in wideband interference rejection. The energy detector with programmable rectifiers provides dynamic-range (DR) scalability, enabling shared use for white-space/interference-level detection and automatic gain control. A prototype chip, fabricated using 90-nm CMOS technology, achieved over 42-dB harmonic rejection including 7th-order component without any external device, a 67-dB gain, a 5-8-dB noise figure, a -11-dBm in-band third-order intercept point, and a +38-dBm second-order intercept point while drawing only 25-37 mA from a 1.2-V power supply. Multi-resolution DR-scalable spectrum sensing with a 0.2-30-MHz detection bandwidth, -83-dBm minimum sensitivity, and a 29-48-dB DR was demonstrated.

A Widely-Tunable Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio

This paper describes a reconfigurable analog baseband (ABB) for a software-defined radio (SDR). A wide variety of filter characteristics needed for SDR can be obtained by a reconfigurable filter based on a newly developed duty-cycle controlled discrete-time transconductor. The ABB, implemented in a 90 nm CMOS process, provides second- and fourth-order Butterworth, Chebyshev, and elliptic responses with bandwidths from 400 kHz to 30 MHz. The chip draws only 12 mA and achieves a P1dB of +7 dBm with a 1.0 V supply. The input-referred integrated in-band noise is 0.31 mVrms and the die area is as small as 0.57 mm2.

A Widely-Tunable, Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio

This paper describes only a low-pass filter configuration, this concept can easily be expanded to cover band-pass filters as well. Since this analog baseband circuit has highly reconfigurable characteristics, is small in size and has low power consumption, it is a strong candidate for utilization as one of the building blocks for SDR transceivers

A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC

All-digital phase-locked loops (ADPLLs) offer the advantages of eliminating the large on-chip passive filter and not suffering from poor low-supply-voltage operation with process scaling [1,2]. However, there is a challenge in achieving low power consumption at the same time as providing the low phase noise required in modern wireless systems like WiFi and WiMAX that have higher-order modulations. Recently, efforts improve phase noise have been accomplished by increasing the time resolution of the time-to-digital converter (TDC) using a gated ring-oscillator structure by using a multipath ring oscillator [3], 2-step structures based on a vernier delay line [4] or a time-amplifier [5,6]. However, these structures require large power consumption because they require many continuously operating high-speed delay-stages.

A 30MHz–2.4GHz CMOS receiver with integrated RF filter and dynamic-range-scalable energy detector for cognitive radio

A 30MHz–2.4GHz CMOS receiver with a highly linear integrated tunable RF filter, as well as with a dynamic-range-scalable RSSI-based energy detector for both whitespace and interference-level sensing, is reported. The test chip, fabricated in 90-nm CMOS process, achieves over 42dB harmonic rejection including seventh-order harmonic without any external device, 67dB gain, 5–8dB NF, +1.7dBm in-band IIP3, and +37dBm IIP2 while drawing only 25–37mA from 1.2V supply.

Cross-Correlation-Based, Phase-Domain Spectrum Sensing With Low-Cost Software-Defined Radio Receivers

This paper describes a highly sensitive spectrum sensing system based on a cross-correlation technique that employs low-cost software-defined radio receivers. By multiplying two data streams received by duplicated receivers and averaging the outputs, a cross-correlation system is able to suppress uncorrelated noise at the cost of measurement time. In this paper, phase-domain detection is proposed to determine whether or not a radio signal is present without any knowledge of signal features. The robustness of our method to noise uncertainty has been verified in both theoretical analyses and simulations. The sensing system has been implemented with low-cost USB tuners and a PC-based digital signal processor. TV-band spectrum sensing has been performed as a demonstration of the system.

Efficient Use of the Spectrum

Demand for efficient operation of radio frequency (RF) devices with limited resources, such as energy and frequency spectrum, is increasing as a variety of wireless applications quickly become more popular. Cognitive radio (CR), which can sense a radio environment and use an unoccupied spectrum, is thought to be a drastic solution for problems such as battery life shortage and/ or spectrum scarcity. This article presents a brief overview of CR systems and describes design challenges for implementing RF integrated circuits (RFICs). A design example of a wideband CMOS receiver for such systems is also discussed.

A 5–9-mw, 0.2–2.5-GHz CMOS low-if receiver for spectrum-sensing cognitive radio sensor networks

A low-power, wideband CMOS receiver for spectrum-sensing cognitive radio sensor networks is presented. The low-IF receiver equipped with an inverter-based LNA-balun and I/Q sub-threshold rectifier enables low-power and high-speed spectrum sensing. For further extension to support higher data-rate radio systems, our local oscillator provides a frequency-dividing function when a low-phase-noise signal source is optionally used. A prototype chip fabricated in a 65-nm CMOS process can support a wide frequency range of 0.2-2.5 GHz with 43-dB maximum gain, 6-dB NF, and -9-dBm IIP3 and only occupies 0.6 mm2 while consuming as low as 5-9 mW at a 0.6-V supply.

Efficient spectrum utilization: Cognitive radio approach

This paper presents a brief overview of cognitive radio applications and discusses design challenges in implementing integrated circuits for spectrum sensing and wideband/reconfigurable transceivers. Our prototype chip of a cognitive radio receiver with multi-resolution, dynamic-range-scalable spectrum sensing capability over a wide frequency range of 30 MHz to 2.4 GHz is also described.