Kazuaki Sogawa

A 125–1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain (Kv) and charge-pump (CP) current over C (ICP/C), the SSCG can realize not only adaptive bandwidth but also process independence at each operating frequency. The innovative point is the adaptive bandwidth control using Kv and ICP/C calibration. This control enabled a test chip to keep a sharp triangular SSC profile while operating over a wide frequency range (125 to 1250 MHz). The variations of VCO gain and CP current are reduced to one third those of the conventional architecture. At 1250 Mbps (625 MHz) the reduction of spectrum peak amplitude is 18.6 dB which is 2.3 dB better than the reduction obtained without calibration.

A -90dBc@10kHz phase noise fractional-N frequency synthesizer with accurate loop bandwidth control circuit

This paper describes a -90dBc@10kHz phase noise fractional-N frequency synthesizer of 110-180MHz output with accurate loop bandwidth control. Stable phase noise is achieved by controlling the bandwidth correctly, even if the PLL uses a noisy but small ring oscillator. Digital controller adjusts VCO gain and time constant of the loop filter. Analog controller compensates temperature variance. Test chip fabricated on 0.13/spl mu/m CMOS process shows stable and good phase noise performance against process and environmental variations.

A -90 dBc@10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit

This paper describes a -90dBc@10kHz phase noise fractional-N frequency synthesizer of 110-180MHz output with accurate loop bandwidth control. Stable phase noise is achieved by controlling the bandwidth correctly, even if the PLL uses a noisy but small ring oscillator. Digital controller adjusts VCO gain and time constant of the loop filter. Analog controller compensates temperature variance. Test chip fabricated on 0.13/spl mu/m CMOS process shows stable and good phase noise performance against process and environmental variations.

An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter

Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. Recently, the widest span of the input frequency has reached 640 times. Although the large divider ratio of the feedback divider relaxes the variation by lowering the VCO gain, the variation of the charge pump current reaches 6400 times in using conventional methods. The new method moderates the variation by changing the gain of the VCO and the capacitance of the loop filter in addition to the charge pump current. Loop filters in the PLL have been evolving along with the improvement of adaptive-biased PLLs. Switched capacitor type loop filters (SC-LPFs) are tolerable to wide variation of the cutoff frequency and preferable for reducing the pattern jitter which appears remarkably on the PLL with high divider ratio. However, the conventional SC-LPF is slightly complex. Thus, the simple 3-phase SC-LPF which realizes the fully flat response has been developed