Masaya Sumita

Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement

The advances in semiconductor manufacturing, EDA tools, and VLSI design technologies are enabling circuit designs with increasingly higher speed and density. However, this trend is causing the on-chip power distribution network to experience larger dynamic voltage fluctuations due to dynamic voltage drop, L di/dt noise, and/or LC resonance. As a result, the analysis of power-integrity, as well as the evaluation and calibration of the analysis methodology, has become a major challenge in designing high-performance circuits. An innovative vectorless dynamic power-ground noise analysis approach is discussed in this paper. This approach addresses full-chip complexity with transistor-level accuracy. This analysis approach demonstrated very good correlation with an on-chip supply noise measurement in 0.13-/spl mu/m CMOS technology, capable of achieving 100 /spl mu/V/100 ps resolution.

Mixed body-bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

There remains a need to improve sub-1-V CMOS VLSIs with respect to variation in transistor behavior. In this paper, to minimize variation in delay and the noise margin of the circuits in processors, we propose several mixed body bias techniques using body bias generation circuits. In these circuits, either the saturation region of the current between source and drain (I/sub ds/) or the threshold voltage (V/sub t/) of PMOS/NMOS is permanently fixed, regardless of temperature range or variation in process. A test chip that featured these body bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well structure. The mixed body bias techniques which keep the I/sub ds/ of the MOS in the decoder and I/O circuits of a register file fixed and maintain the V/sub t/ of the MOS in both the memory cell and domino circuits of the register file fixed resulted in positive temperature dependence of delay from -40 /spl deg/C to 125 /spl deg/C, 85% reduction of the delay variation compared with normal body bias (NBB) at V/sub DD/ = 0.8 V. In addition, the results using these techniques show a 100-mV improvement in lower operating voltage compared with NBB at -40 /spl deg/C on a 4-kb SRAM.

Mixed body-bias techniques with fixed Vt and Ids generation circuits

In sub 1 V CMOS VLSIs, the authors proposed a new body bias generation circuits in which Ids and Vt of pMOS/nMOS become always fixed. The mixed body bias techniques result in positive temperature dependence of the delay, 85% reduction of the delay variation, and 75% improvement of power consumption of SRAM on a mobile processor.

High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar

With scaling process generation, power management techniques are more significant. Body bias techniques are useful for the solutions. We propose a high resolution body bias generation circuit which supplies optimal body bias in both the active and standby mode. By using this circuit, the adjustment accuracy of threshold voltage (Vt) in the active mode was improved about 4.1 times of the conventional circuits at 0.6V forward body bias condition. In addition, for standby mode, when 128 kByte SRAM was supplied back body bias by this generator, the off-state leakage current was reduced to 50% of a fixed back body bias.

Multi-Ported Register File for Reducing the Impact of PVT Variation

We have developed a 32-bit, 32-word, and 9-read, 7-write ported register file. This register file has several circuits and techniques for reducing the impact of process variation that is marked in recent process technologies, voltage variation, and temperature variation, so called PVT variation. We describe these circuits and techniques in detail, and confirm their effects by simulation and measurement of the test chip.