Yoichi Tamaki

A 64 GHz Si bipolar transistor using in-situ phosphorus doped polysilicon emitter technology

A high-performance bipolar transistor technology has been developed for emitter formation using in-situ phosphorus doped polysilicon (IDP). Using this technology, a Si bipolar transistor was designed with a shallow emitter junction, an ultra-high current gain, and a cutoff frequency (f/sub T/) of 64 GHz. Furthermore, the product of f/sub T/ and BV ceo of 200 GHz-V has been achieved. This value is nearly equal to the physical limitation for homojunction silicon transistors. The technology reported here is believed to be very promising for future fabrication of ultra-high-speed high-density bipolar and BiCMOS VLSIs.<<ETX>>

29 ps ECL circuits using U-groove isolated SICOS technology

A 0.5- mu m SICOS (sidewall base contact structure) technology is discussed. U-groove isolation technology and 0.5- mu m fabrication technology reduce the transistor size to 60 mu m/sup 2/. The use of a reduced-resistance base polysilicon electrode and a shallow epitaxial layer improves the emitter-coupled logic (ECL) gate delay time by 20% and 30%, respectively. A typical gate delay time of 29 ps and a minimum gate delay time of 27 ps at a switching current of 1.2 mA and an emitter size of 0.4 mu m*2.4 mu m were realized. This U-groove isolated SICOS device is suitable for very-high-speed VLSIs.<<ETX>>

In situ phosphorus-doped polysilicon emitter technology for very high-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-/spl mu/m emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed.

Very-high-speed silicon bipolar transistors with in-situ doped polysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B/sub 2/H/sub 6/. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time. >

Hetero-emitter-like characteristics of phosphorus doped polysilicon emitter transistors. Part I: band structure in the polysilicon emitter obtained from electrical measurements

This paper reports on the cause of hetero-emitter-like characteristics recently discovered for a phosphorus doped poly-Si emitter transistor, the poly-Si emitter of which is crystallized from an in-situ phosphorus doped amorphous Si film. The band structure in the poly-Si emitter is investigated using (1) the transistor characteristics and (2) the I-V characteristics of the interface between the poly-Si emitter layer and the Si substrate. As a result, a new kind of potential barriers are observed on the conduction band and the valence band at the interface. The potential barrier on the valence band is proved to be the origin of the hetero-emitter-like characteristics. According to the I-V characteristics of the interface, the formation of the barriers is probably due to band discontinuity at the interface. >

The effect of thin interfacial oxides on the electrical characteristics of silicon bipolar devices

The effect of thin interfacial oxides on the impurity diffusion from polysilicon to the silicon substrate has been studied in detail. Polysilicon films were deposited on the silicon substrate in two different process conditions to control the thickness of interfacial oxides. Results show that the presence of about 1-nm-thick oxides retarded the impurity diffusion by about 10 nm and an increase of the sheet resistance of about 10 percent has been observed. Bipolar devices, which are sensitive to the impurity profiles, were fabricated with identical processing apart from the polysilicon deposition conditions. A detailed analysis of their electrical characteristics shows the difference of collector current components and hence the increase of current gain by about two times. These results indicate that the effect of interfacial oxides on the impurity profile is expressed by the segregation coefficientm, which is the ratio of Csi/CpolySiat the interface. The sensitivity ofmfor the device characteristics was calculated by a process-device simulator, and it is demonstrated that the current gain is a strong function ofmfor shallow emitters.

A 0.5- mu m very-high-speed silicon bipolar devices technology U-groove-isolated SICOS

A 0.5- mu m high-performance silicon bipolar technology is developed and a very-high-speed emitter-coupled-logic (ECL) circuit is demonstrated. Circuits are fabricated with a 0.5- mu m SICOS (sidewall base contact structure) technology featuring U-groove isolation, a shallow impurity profile, and reduced base resistance. A U-groove-isolated SICOS structure is realized by the new self-alignment technology using the double polysilicon planarization method. To reduce the extrinsic base resistance, a large-grain base polysilicon is grown from the amorphous silicon layer. A greatly reduced substrate capacitance and small base resistance are obtained. Using these technologies, a minimum ECL gate delay of 27 ps at F/sub in/=1 is realized. A 20-ps ECL gate will be possible in a device having a smaller emitter and the optimal graft base depth. >

SPOTEC-a sub-10- mu m/sup 2/ bipolar transistor structure using fully self-aligned sidewall polycide base technology

A novel structure for high-speed Si bipolar transistors has been developed and a 9.4- mu m/sup 2/ transistor is demonstrated. Transistors are fabricated with a new sidewall polycide base electrode technology (SPOTEC), narrow W plug metallization, narrow U-groove isolation, and 0.3- mu m lithography using an e-beam direct writing technique. SPOTEC is used to reduce the base electrode area. That is, CVD (chemical vapor deposited) W is selectively deposited on a sidewall surface of the polysilicon and is silicided. This technology makes a narrow and low-resistance base electrode (0.4 mu m wide and 10 Omega / Square Operator ) possible. The collector electrode is directly contacted on an n/sup +/ buried layer to reduce its area. The contact hole is filled with a low-resistance W plug by using selective W CVD technology. To reduce the isolation area, a narrow, deep U-groove is etched and refilled with CVD SiO/sub 2/. These four key techniques reduce the transistor area to less than 10 mu m/sup 2/. The shallow E-B junctions are formed using low-energy ion implantation and RTA (rapid thermal annealing). A high cutoff frequency of 38 GHz and small junction capacitances are obtained.<<ETX>>

U-Groove Isolation Technology for High Density Bipolar LSI's

A new isolation technology for high packing density bipolar LSIs has been developed. This technology is composed of two main processes, U-groove formation and U-groove filling. The U-grooves are formed by anisotropic etching and reactive sputter etching of silicon. The grooves, covered with a composite Si3N4/SiO2 layer, are filled with polysilicon. Surface planarity is achieved by selective etching of the polysilicon. An ECL integrated circuit fabricated using the U-groove isolation (U-Iso) technology exibits a minimum isolation distance of 3 µm, an isolation voltage of 50 V, an isolation capacitance of 0.2 pF, and a propagation delay time, measured by ringoscillator, of 0.3 ns/gate.

Advanced process device technology for 0.3- mu m high-performance bipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3- mu m bipolar LSIs. Fabricated 0.5- mu m U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 mu m/sup 2/, and they have an isolation width of 2.0 mu m, a minimum emitter width of 0.2 mu m, a maximum cutoff frequency (f/sub T/) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3- mu m bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f/sub T/ and base resistance is also discussed. >