Hariprasath Venkatram

A 10-b Ternary SAR ADC With Quantization Time Information Utilization

The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC) with quantization time information utilization is proposed. The TSAR examines the transient information of a typical dynamic SAR voltage comparator to provide accuracy, speed, and power benefits. Full half-bit redundancy is shown, allowing for residue shaping which provides an additional 6 dB of signal-to-quantization-noise ratio (SQNR). Synchronous quantizer speed enhancements allow for a shorter worst case conversion time. An increased monotonicity switching algorithm, stage skipping due to reference grouping, and SAR logic modifications minimize overall dynamic energy. The architecture has been shown to reduce capacitor array switching power consumption and digital-to-analog converter (DAC) driver power by about 60% in a mismatch limited SAR, reduce comparator activity by about 20%, and require only 8.03 average comparisons and 6.53 average DAC movements for a 10-b ADC output word. A prototype is fabricated in 0.13-μm CMOS employing on-chip statistical time reference calibration, supply variability from 0.8 to 1.2 V, and small input signal power scaling. The chip consumes 84 μ W at 8 MHz with an effective number of bits of 9.3 for a figure of merit of 16.9 fJ/C-S for the 10-b prototype and 10.0 fJ/C-S for a 12-b enhanced prototype chip.

A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information

In this paper, a Nyquist ADC with a time-based pipelined TDC is proposed. In the proposed ADC, the first pipeline stage incorporates both residue amplification and a V-T conversion with high accuracy, efficiently realized by a low gain amplifier with only 24 dB dc gain. Furthermore, adding to power efficiency, a hybrid time-domain pipeline stage based on simple charge pump and capacitor DAC in its backend stages is also proposed. Using the right combination of voltage and time domain information, the proposed ADC architecture benefits from improved resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13 μm CMOS demonstrate peak SNDR of 69.3 dB at 6.38 mW power and 70 MHz sampling frequency. The FOM based on peak SNDR is 38.2 fJ/conversion-step.

Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm

The early reset merged capacitor switching algorithm (EMCS) is proposed as an energy reducing switching technique for a binary weighted, capacitive successive approximation (SAR) analog to digital converter (ADC). The method uses the merged capacitor switching (MCS) architecture and optimizes the use of the VCM level during the SAR conversion. This algorithm can reduce switching power by over 12% with no additional DAC driver activity when compared to the MCS scheme. The MCS and EMCS approaches are analyzed mathematically and the EMCS energy consumption is shown to be lower than or equal to that of the MCS technique for every digital code. Static linearity improvements for this structure are also shown with the integral non-linearity (INL) reducing by a factor of two due to the utilization of the MCS three level DAC. The EMCS implementation methodology is also described.

A 10b Ternary SAR ADC with decision time quantization based redundancy

The design of a Ternary Successive Approximation ADC (TSAR) with decision time quantization is proposed. The TSAR examines the transient information of the typical SAR comparator to provide full half-bit redundancy, an increased monotonicity switching algorithm, speed enhancements without inherent metastability, residue shaping effects, and stage skipping. A prototype is fabricated in 0.13μm CMOS employing on-chip statistical time reference calibration and supply variability from 0.8 to 1.2V. The chip consumes 84μW at 8 MHz for a FOM of 16fJ/C-S.

Blind background calibration of harmonic distortion based on selective sampling

This paper proposes a blind calibration algorithm for suppressing harmonic distortion in analog to digital converters (ADCs). The proposed algorithm does not need any external calibration signal and is first of its kind. The proposed algorithm relies on the properties of downsampling and orthogonality of sinusoidal signals to estimate the harmonic distortion coefficients. The algorithm can be operated in both foreground and background modes to remove even and odd harmonics simultaneously. The algorithm is demonstrated on a first-order ring oscillator based ΔΣ ADC, whose performance is harmonic distortion limited. Built in 0.13μm, the algorithm improves the SNDR of the ADC by 39dB while improving SFDR by 45 dB.

Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling

This paper proposes a blind calibration algorithm for suppressing nonlinearity in analog-to-digital converters (ADCs). The proposed algorithm does not need any external calibration signal and is first of its kind. The proposed algorithm relies on the properties of downsampling and orthogonality of sinusoidal signals to estimate the nonlinearity coefficients present in the system and can be operated to remove even and odd order nonlinearities simultaneously. The working of the algorithm is demonstrated on a first-order ring oscillator based ΔΣ ADC, whose performance is limited due to the nonlinearity present in its system. Built in 0.13 μm CMOS, the algorithm improves the SNDR of the ADC by 39 dB, while improving SFDR by 45 dB.

A 62mW stereo class-G headphone driver with 108dB dynamic range and 600µA/channel quiescent current

Mobile and portable devices like smartphones and tablets require headphone drivers that consume the lowest possible levels of quiescent current while operating directly from available battery voltages. Key headphone performance parameters for these devices are high dynamic range, high output power and low pop-and-click noise. This paper demonstrates a class-G headphone driver with 600μA/channel quiescent current that operates over a 2.95 to 4.5V supply range, which is compatible with Li-Ion batteries. This headphone driver achieves 108dB dynamic range, 62mW output power and 50μV pop-and-click noise.

Parallel gain enhancement technique for switched-capacitor circuits

This paper presents a unified classification model for gain enhancement techniques used in the design of high performance amplifiers. A parallel gain enhancement technique is proposed for switched capacitor circuits which combine the best features of the existing gain enhancement techniques found in continuous-time and discrete-time amplifiers. This technique utilizes two dependent closed loop amplifiers to enhance the open loop DC gain of the main amplifier. This replicated parallel gain enhancement (RPGE) technique enables a very high DC gain amplifier with an improved harmonic distortion performance. A proof of concept pipeline ADC in a 0.18 um CMOS process using RPGE technique achieves 75 dB SNDR, 91 dB SFDR, -87 dB THD at 20 MS/s. The measured 13 bit DNL and INL is +0.75/-0.36 and +0.88/-0.92 LSB respectively. The ADC operates from a supply voltage of 1.3 V, consumes 5.9 mW, occupies 3.06 mm2 and achieves a figure of merit of 65 fJ/CS.

Detection and Correction Methods for Single Event Effects in Analog to Digital Converters

This paper presents detection and correction methods for single event effects in analog to digital converters. Multi-path ADC based detection method is proposed for single event effects and bit error rate. Two correction schemes are proposed for single event effects based on multi-path ADC structure. Two-path ADC based detection scheme with skip and fill algorithm based correction scheme. Three-path ADC based detection scheme with majority voting based correction scheme. Advantages and limitations of both the methods are presented with simulation results. In particular, the three-path ADC can detect and correct for single event effects independent of repetition rate, magnitude of single event effects and the choice of data converter architecture. In three path ADC technique, the accuracy degradation is less than 1.7 dB or 0.28 bit for the Nyquist bandwidth for single event effects. Bit-Error Rate (BER) is effectively squared for three-path ADC as compared to a conventional ADC.

Least Mean Square calibration method for VCO non-linearity

This paper introduces Least Mean Square (LMS) based calibration technique for Voltage Controlled Oscillator (VCO) based ADC. The VCO provides an inherent sinc filtering for the input voltage. The harmonics are also attenuated by the corresponding sinc functions. An 8-bit VCO based ADC was simulated with a 5-bit linear VCO. This ADC was calibrated using LMS algorithm. After calibration, SNDR is close to the ideal 8-bit converter.