Kazumasa Sunouchi

Memory design using one-transistor gain cell on SOI

A 512 kb DRAM has a 7F/sup 2/ one-transistor gain cell (F=0.18 /spl mu/m) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.

Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's

A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed. >

High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

A novel transistor with compact structure has been developed for MOS devices. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. For example, the occupied area of a CMOS inverter can be shrunk to 50% of that using planar transistors. The other advantages are steep cutoff characteristics, very small substrate bias effects, and high reliability. These features are due to the unique structure, which results in greater gate controllability and in electric field relaxation at the drain edge.<<ETX>>

A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

A novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs). In the SGT cell structure, a transfer gate and a capacitor electrode surround a pillar silicon island. Contact of the bit line is made on top of the silicon pillar. All devices for a memory cell are located in one silicon pillar. Each silicon pillar is isolated by matrixlike trenches. Therefore, there is no intercell leakage current even in small cell-to-cell spacing. The SGT cell can achieve an extremely small cell size of 1.2 mu m/sup 2/ and a large capacitance of 30 fF using a relaxed design rule of 0.5 mu m. The cell has been fabricated and its functionality confirmed.<<ETX>>

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGTs) For ultra high density DRAMs. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGTs connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V/sub cc/ margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL. >

Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode surrounds the crowded multipillar silicon islands. Because all the sidewalls of the pillars are used effectively as the transistor channel, the M-SGT has a high-shrinkage feature. The area occupied by the M-SGT can be shrunk to less than 30% of that occupied by the planar transistor. The small occupied area and the mesh-structured gate electrode lead to the small junction capacitance and the small gate electrode RC delay, resulting in high-speed operation. The fabrication of the M-SGT CMOS inverter chain is discussed. The propagation delay reduces to 40%, compared with the planar transistor inverter chain. >

High speed and compact CMOS circuits with multi-pillar surrounding gate transistors

Summary form only given. In order to overcome the scaling limitations on planar transistors for future LSIs, the authors propose a novel surrounding gate transistor (SGT), whose gate electrode surrounds multipillar silicon islands. The new SGT offers large drain currents even in a very small occupied area. The large channel width is achieved by using all the sidewalls of the crowded multipillar silicon islands as the channel regions. Owing to this multichannel structure, a transistor with extremely small occupied area and sufficient drivability can be obtained. The small occupied area and the mesh-structured gate electrode lead to small gate electrode RC delay and small junction capacitance, resulting in very high-speed operation, contrary to the cases of the planar transistor and the conventional SGT. A new SGT CMOS inverter chain was fabricated. The propagation delay is reduced to 20% of that for the case of the planar transistors. This new SGT is extremely attractive for future high-speed ULSI devices. >

Process integration for 64 M DRAM using an asymmetrical stacked trench capacitor (AST) cell

The key points of sub-half-micron CMOS technologies for 64-Mb DRAM fabrication are described. The main features of the technologies are (1) an asymmetrical stacked trench capacitor (AST) cell, (2) localized channel implantation through the field oxide (LIF), and (3) a 0.4- mu m transistor with LDD (lightly doped drain) n/sup -/ impurity of arsenic. The lithographic levels are 0.4 mu m for critical layers. achieved using a KrF excimer laser stepper. The AST cell has a stacked capacitor in a trench; the trenches are located asymmetrically with respect to each other. A small cell area of 1.53 mu m/sup 2/ has been achieved by adopting the LIF isolation and the As LDD transistor for the AST cell. An experimental 64-Mb DRAM chip has been successfully fabricated using these technologies.<<ETX>>

A surrounding isolation-merged plate electrode (SIMPLE) cell with checkered layout for 256 Mbit DRAMs and beyond

The authors describe a novel cell structure called a surrounding isolation merged plate electrode (SIMPLE) cell. In this cell, close-packed silicon pillars are laid out checker-wise, and a thin isolation-merged plate electrode surrounds the pillars. This cell structure leads to cell area reduction to 50%, trench depth reduction to 50%, and planarization and process step reduction compared with the conventional trench type cell. Using the design rule of 64 Mbit DRAM (dynamic RAM) (0.35 mu m), the SIMPLE cell can achieve a cell area of 256 Mbit DRAM (0.5 mu m/sup 2/). The SIMPLE cell is an attractive candidate for 256 Mbit DRAMs and beyond.<<ETX>>

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

The dependence of MOSFET gate controllability on the field-isolation scheme is investigated using three-dimensional simulation. It is found that a fully-recessed-oxide (trench) isolated MOSFET has a steep subthreshold characteristic and high transconductance in comparison with a nonrecessed device. These features result from the small depletion capacitance due to the crowding of the gates fringing field at the channel edge. It is also found that the gate and diffused line capacitances in the case of fully-recessed-oxide isolation are small, so that high switching speed operation can be expected. These features are enhanced with a reduction in the channel width, especially for lower-submicrometer-width MOSFETs. A drawback of a fully-recessed-oxide MOSFETs is its low threshold voltage. However, the leakage current is not as large as that inferred from the inverse narrow-channel effect because of its steep subthreshold characteristic. Several countermeasures for this low threshold voltage are discussed. >