Kazunari Inoue

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.

A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture

A 4.5 Mb dynamic ternary CAM (DTCAM) is designed in 0.13 /spl mu/m embedded DRAM technology. A performance of 143 M searches/sec is achieved at a power dissipation of 1.1 W and on a small silicon area of 32 mm/sup 2/. A 3.6-times yield improvement is estimated by employing pipelined hierarchical searching and row/column-shift redundancy.

Minimization of ACL storage by adding minimal hardware of range matching and logical gates to TCAM

Ternary content addressable memory (TCAM) is a special type of memory used in routers in order to achieve high speed packet classification. The classification is performed using the five fields in an access control list (ACL), port numbers being one of them. Since port numbers that are expressed in ranges require multiple entries in storage, this results in an increased cost of hardware. In this paper we propose a method to reduce the number of entries when expressing ranges in TCAM. We use range matching devices integrated within the TCAMpsilas control logic and optimized prefix expansion that utilizes logical AND and NOT gates in the TCAM array itself. In addition, we use real data of an existing network to show that the proposed architecture can store the ACL in an efficient way.

Hardware implementation of fast forwarding engine using standard memory and dedicated circuit

Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of cost of hardware and cost of power, which limits it deploying large amounts of capacity. In this paper, we propose a new hardware architecture for a fast forwarding engine that fundamentally solves the potential problems of TCAM. We also develop a hardware design for our architecture. Our results show that the proposed hardware reduces the costs of hardware resources needed and power consumption into 62% and 52%, respectively.

A single-chip CMOS speech synthesis chip

A single chip CMOS speech synthesizer with 32Kb of speech data ROM and a D/A converter will be discussed. Design is based on a time domain algorithm that distinguishes between voiced and unvoiced utterances. The chip can produce about 35 words of high quality speech.

Design of a high-speed content-centric-networking router using content addressable memory

Content-centric networking (CCN) is an innovative network architecture that is being considered as a successor to the Internet. To implement the novel technologies, however, requires routers with performance far superior to that offered by todays Internet routers. Although many researchers have proposed various router components, such as caching and name lookup mechanisms, there are few router-level designs incorporating all the necessary components. The design and evaluation of a complete router is the primary contribution of this paper. We provide a concrete hardware design for a router model incorporating two entities that we propose. One of these entities is the name lookup entity (NLE), which looks up a name address within a few cycles from content addressable memory (CAM) by use of a Bloom filter; the other is the interest count entity (ICE), which supports to select content worth caching. Our contributions are (1) presenting a proper algorithm for looking up and matching name addresses in CCN communication, (2) proposing a method to process CCN packets in a way that achieves high throughput and very low latency, and (3) demonstrating performance and cost on the basis of a concrete hardware design.

2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving

Recently, energy consumption of routers has become a serious problem, hence power reduction is an urgent and important challenge. Existing routers always work 100% of their potentials regardless of required performance, such as volume of input traffic. However, semiconductor devices such as lookup logics, buffers, fabrics are not always fully utilized. In particular, the occupancy of packet buffer is very low in many cases, especially in core routers, which leads to unnecessary consumption of electric power. To solve this problem, a new buffer architecture called Sliced Packet Buffer was proposed. Dividing a whole buffer into multiple sub buffers (called slices) at the LSI level enables to control power management independently according to its occupancy. However, input traffic rate is another parameter for further power savings, which was not considered so far. In this paper, we propose a Two Dimensional Sliced Packet Buffer which enables power management according to not only the buffer occupancy but also the traffic volume. We also propose a model of accurate performance evaluation on energy consumption in the granularity of operational instruction. Through trace-driven simulations with real traffic, we show that our proposed packet buffer can reduce an average 66% of power consumption when an average input rate is 30%.

A slice structure using the management of network traffic prediction for green IT

Maintaining complete network service with the current infrastructure is an urgent task due to continuous growth in network traffic. It is expected that the energy consumption of network routers may become a global environmental problem, and therefore, research and development into power reduction is well desired. Our group proposes a unique structure embedded into routers, which consists of multiple slices and is dynamically controlled by the prediction of network traffic flow. In this paper, we examine this slice control and LSI architecture, and show the validity of a router. Also, the simulation used in this study is based on the true traffic in the university.

A Single CMOS Speech Synthesis Chip and New Synthesis Techniques

A single CMOS speech synthesis LSI, organized as a special purpose microcomputer containing program ROM, RAM, 32K of speech data ROM, and a D/A converter is described in this paper. The chip utilizes new speech synthesis techniques to generate high quality speech, reproducing the natural inflection and intonation of the speaker, and has been used to produce speech at a bit rate of about 3 kbits/s.

Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure

Packet classification has become increasingly complex and important to network equipment intended for future use. A recent trend to achieve complex packet classification is to use software-based methods, which tend to be slower than hardware-based methods. For search, this typically means using ternary content-addressable memory (TCAM) to make classification feasible. However, TCAM is not well-suited to the long (in bits) and sparse rules used for running advanced applications that require complicated classification. We propose a multi-dimension search engine (MDSE) that is optimized for use with long, sparse rules, and we propose a multi-dimensional TCAM scheme, which is an MDSE constructed to operate on TCAM. Through fine-grained simulations with real traffic, we show that our proposed search engine can reduce the power consumed by network equipment by about 85%.