Kazutami Arimoto

A built-in Hamming code ECC circuit for DRAMs

An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique. >

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q/sub s/) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-/spl mu/m CMOS process. The chip size is 7.9/spl times/16.7 mm/sup 2/ and cell size is 1.35/spl times/2.8 /spl mu/m/sup 2/.

A new array architecture for parallel testing in VLSI memories

The authors describe a novel array architecture and its application to a 16-Mb DRAM (dynamic random-access memory) suitable for the line mode test (LMT) with test circuits consisting of a multipurpose register (MPR) and a comparator. The LMT can test all memory cells connected to a word line simultaneously. Testing with random patterns along a word line is easily realized by using the MPR as a pattern register after setting random test data in the MPR. Test time is reduced to approximately 1/1000. Owing to the MPR, the present LMT can achieve flexible testing with high fault coverage. The excess area penalty due to the circuits for the LMT is suppressed within 0.5% in application to the 16-Mb DRAM.<<ETX>>

A 90ns 4Mb DRAM in a 300 mil DIP

A 4Mb DRAM employing a folded-bitline adaptive sidewall - isolated capacitance cell with 2μm deep trenches, a 72.3mm2chip size and 90ns access time will be described. Also incorporated are full bonding options for 4Mb×1 or 1Mb×4 organizations and for static column or page-mode operation.

A circuit design of intelligent cache DRAM with automatic write-back capability

An intelligent cache based on a distributed architecture that consists of a hierarchy of three memory sections-DRAM (dynamic RAM), SRAM (static RAM), and CAM (content addressable memory) as an on-chip tag-is reported. The test device of the memory core is fabricated in a 0.6 mu m double-metal CMOS standard DRAM process, and the CAM matrix and control logic are embedded in the array. The array architecture can be applied to 16-Mb DRAM with less than 12% of the chip overhead. In addition to the tag, the array embedded CAM matrix supports a write-back function that provides a short read/write cycle time. The cache DRAM also has pin compatibility with address nonmultiplexed memories. By achieving a reasonable hit ratio (90%), this cache DRAM provides a high-performance intelligent main memory with a 12 ns(hit)/34 ns(average) cycle time and 55 mA (at 25 MHz) operating current. >

An embedded DRAM hybrid macro with auto signal management and enhanced-on-chip tester

Embedded DRAM (eDRAM) macros have been proposed as away to achieve the low power and wide bandwidth required by graphic controllers, network systems, and mobile systems. Currently, these applications require a reduction of design turn-around time (TAT) for the various specifications, as well as lower-voltage operation. Conventional eDRAM is generated by placement of hardware macros that are designed beforehand. The hardware macro restricts eDRAM specifications, and many hardware macros are necessary to support the demands of different customers. An eDRAM architecture that provides only the interface component as a software macro, i.e., hardware description language (HDL), has been recently reported. However, in this architecture, adjusting of control signal delays and differing control circuits are necessary for each memory configuration. The architecture reported here provides reduction of design TAT, more than 120 k eDRAM configurations, 1.2 V (100 MHz) to 1.8 V (200 MHz) operation, and a flexible interface. In addition, an enhanced on-chip tester tests the various eDRAM macros, reducing test time to 1/64 with a simultaneous 512 b I/O pass/failjudgment, and performs repair analysis at speed testing conditions.

A speed-enhanced DRAM array architecture with embedded ECC

An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes practical array-embedded error checking and correcting (ECC) with little area penalty and no access overhead in the page mode. The array architecture is applied to a scaled-down 16-Mb DRAM and has achieved high performance. >

A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write

A high density memory (HDRAM) for SoC with SRAM interface is described. This macro achieves no-wait fast random-cycle operation owing to a sense-synchronized read/write scheme. A 4Mb test device is fabricated in a 0.15/spl mu/m process and achieves 143MHz operation. Its size and standby power are 4.59mm/sup 2/ and 92mW, which are 30% and 4.8%, respectively, of an embedded SRAM macro fabricated identically.

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write

This paper describes a 4-Mb embedded DRAM macro using novel fast random cycle architecture with sense-synchronized read/write (SSR/SSW). The test chip has been fabricated with a 0.15-/spl mu/m logic-based embedded DRAM process and the 1.5-V 143-MHz no-wait row random access operation has been confirmed. Data retention power is suppressed to 92 /spl mu/W owing to the hierarchical power supply and SSR. The macro size is 4.59 mm/sup 2/. The cell occupation ratio of the macro is 46%, which is the same as that of a conventional embedded DRAM macro. The macro size and the data retention power are 30% and 4.6%, respectively, of a 4-Mb embedded SRAM macro fabricated by an identical process.

SOI-DRAM circuit technologies for low power high speed multi-giga scale memories

New SOI-DRAM circuits were proposed and described. The body bias controlling technique, especially super body-synchronous sensing, is found to be suitable for low voltage operation. A new type of redundancy enables Icc2 reduction and promises high yield against the increasing standby current failure.