Kazuyasu Fujishima

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

For future ULSI DRAMs beyond the 256 Mb generation, several circuit techniques and memory cell structures have been proposed to meet the requirement of high performance at low voltage. These solutions frequently involve complicated processing steps and/or the ultimate limitations of current Si-MOS devices. DRAM on silicon on insulator (SOI) substrate is a more simple solution to the problem. Thin-film SOI structures with isolation by implanted oxygen (SIMOX) process are under investigation for SRAM and logic. A SOI-DRAM test device with 100 nm thick SOI film has been fabricated in 0.5 /spl mu/m CMOS/SIMOX technology. With this 64 kb SOI-DRAM the bit-line to memory cell capacitance ratio Cb/Cs is reduced by 25% compared with the reference bulk-Si DRAM, because of the decreased junction capacitance. RAS access time tRAC is 70 ns at 2.7 VVcc, as fast as the equivalent bulk-Si device at 4 VVcc. The clock timing in this DRAM is not optimized, so access time should improve with well-tuned clocks. The boosted-level generator with body-contact structure enhances the upper Vcc margin and the reduced body-effect of sense-amplifier transistors improves the lower Vcc margin. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. >

High-performance embedded SOI DRAM architecture for the low-power supply

This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can he relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage, Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM.

A 90ns 1Mb DRAM with multi-bit test mode

A 1Mb DRAM using a half Vcc biased memory cell with a reduced electric field of 2MV/cm will be reported. A shared sense amplifier design and a continous nibble mode are also included. Additionally, a test pin allows testing as a 256K×4 memory. Die is 65mm2.

An experimental 256-Mb DRAM with boosted sense-ground scheme

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAMs to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (boosted sense-ground) scheme for data retention and FOGOS (folded global and open segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm/sup 2/ and a performance of 34 ns access time. >

A circuit design of intelligent CDRAM with automatic write back capability

The authors describe a unique intelligent memory based on a distributed CDRAM (cache DRAM) architecture, which consists of three hierarchical memory sections, DRAM, SRAM, and CAM, that constitute on-chip TAG. This architecture provides a high-performance intelligent main memory and a pin compatibility with high-speed address nonmultiplexed memories (DRAM, SRAM, and pseudo-SRAM). This RAM can be fabricated by the standard CMOS DRAM process with little area penalty. The intelligent CDRAM with an automatic write-back function can realize a short average read/write cycle time. The write-back operation without a complex controller minimizes the write cycle time drastically compared with write through

A 256K dynamic RAM with page-nibble mode

A 5-V 256K /spl times/ 1 bit NMOS dynamic RAM with page-nibble mode is designed and fabricated using 2-/spl mu/m design rules and folded bit-line configuration. Molybdenum disilicided polysilicon is used as the second-level gate to reduce the word-line signal delay. A large 98 /spl mu/m/SUP 2/ cell with Hi-C structure stores the signal charge of 210 fC and provides this memory with wide operating margin. The device is immune to voltage bumping and uses laser programmable redundancy. Typical RAS/CAS access times are 80 ns/40 ns. An average operating current of 50 mA with 80 mA peak at 230 ns cycle time and standby current of 2 mA are achieved.

A reliable 1-Mbit DRAM with a multi-bit-test mode

A single 50V supply 1-Mb DRAM using a half V/SUB cc/ biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide world-line technology.

Automatic Voltage-swing Reduction (avr) Scheme For Ultra Low Power Drams

LIntroduction Recently, low power DRAMs[l-3] are strongly needed for handheld machines. To reduce the data-retention current, the DRAMs should have 1)long data-retention time, 2)low active current for a refresh operation, and 3)low stand-by current. This paper describes new current saving techniques for the high-density DRAMs. The combination of the Voltage-DownConvertor (VDC) and Boosted-SenseGround (BSG) scheme[4] achieves the low active current b reducing

A 100ns 256K DRAM with page-nibble mode

This paper will report on a 256K×1b 100ns access time DRAM which functions in both page and nibble mode, distinguished internally by theoverline{CAS}precharge time. The device is immune to voltage bumping and uses laser programmable redundancy.

A divided/shared bitline sensing scheme for 64 Mb DRAM core

New high-density DRAM core designs based on a new divided bitline sensing principle are proposed and their performance is estimated. These designs can achieve a high-density memory cell array and can also overcome problems of the scaled memory array. These designs are promising candidates for 64-Mb DRAM and beyond