Hiroki Shimano

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory

A twin-transistor random access memory (TTRAM) can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. Enhanced TTRAM (ET2RAM) applies the actively body-bias control technique to realize the low voltage array operation, and never require the negative voltage source. The ET2RAM can realize both 263 MHz at 0.8 V and 10.2 mW at 0.5 V random-cycle operation, higher cell efficiency, and process scalability. It also provides the simple control method suitable for the unified macro for system-level power management SoC with keeping the merits of TTRAM as CMOS compatibility

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs

Several high-density SOI memory technologies utilizing the body floating effects have been proposed. Conditions needed for SoC memory IPs for many kinds of applications are not only performance but also suitability for platform technologies. We had reported TTRAM (Twin Transistor RAM) and (Enhanced TTRAM) which are high-density capacitorless SOI-CMOS compatible memory IPs. A platform design methodology becomes the mainstream, providing QTAT and low-cost design. Now, we have upgraded the with application-required functions called scalable TTRAM. This memory IP can be applied to many kinds of applications using the verify control technique with compact actively body-bias controlled (ABC) sense amplifier, and the unique test mode functions have also been proposed for practical usage. The test chip of 4 Mbit macro fabricated with 90 nm standard SOI CMOS achieves performance of 263 MHz high-speed random access, 79 mW/4 Mb lower active power dissipation, 453 MHz data transfer of page/burst mode and lower stand-by current mode of 5 s data retention time. The scalable TTRAM can play the role of on-chip SoC memory IPs, for example, in consumer, mobile, and MPU/game applications.

A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform

The advanced-DFM RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability(@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 cell/bit with the complementary dynamic memory operation and has the 1 cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (sense synchronized write) peripheral circuit technologies are also adopted for the low voltage and FV controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.