Kazutoshi Hirayama

Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester

Semiconductor memory device including programmable mode selection circuitry

Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same

Semiconductor memory device having redundant circuit and method of testing to see whether or not redundant circuit is used therein

Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test

INPUT CIRCUIT FOR LOGIC CIRCUIT HAVING NODE AND OPERATING METHOD THEREFOR

Semiconductor memory device carrying out reading and writing operations in order in one operating cycle and operating method therefor

Semiconductor memory device with precharging voltage level unchanged by defective memory cell

Internal voltage generating circuit, semiconductor memory device, and method of measuring current consumption, capable of measuring current consumption without cutting wire

Semiconductor memory with redundancy circuit - has standby memory cell field whose cells can replace respective normal cells and has external signal indicating state of selection controller