Hiroyuki Kanbara

Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density. >

Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment. Irradiation tests also show the correlation between the number of sensitive bits and the mean time to failure. Furthermore, the temporal error rate of an example application due to soft errors in the datapath were measured and demonstrated for reliability-aware mapping.

Operational amplifier compilation with performance optimization

A design methodology is described for analog circuits in which topological design is followed by simultaneous device sizing and layout design. By merging circuit and layout design into a single design process, analog circuits can be optimally designed, taking layout parasitics fully into account. Based on the methodology, a CMOS operational amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A novel procedural layout technique is used for generating compact and practical layouts. A nonlinear optimization method is applied for device sizing that relies on the results of simulations based on the circuit extracted from the layout. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density

High-Level Synthesis of Software Function Calls

This letter presents a novel framework in high-level synthesis where hardware modules synthesized from functions in a given ANSI-C program can call the other software functions in the program. This enables high-level synthesis from C programs that contains calls to hard-to-synthesize functions, such as dynamic memory management, I/O request, or very large and complex functions. A single-thread implementation scheme is shown, whose correctness has been verified through register transfer level simulation.

Radiation-Induced Soft Errors

We will begin by a quick but thorough look at the effects of faults, errors and failures, caused by terrestrial neutrons originating from cosmic rays, on the terrestrial electronic systems in the variety of industries. Mitigation measures, taken at various levels of design hierarchy from physical to systems level against neutron-induced adverse effects, are then introduced. Challenges for retaining robustness under future technology development are also discussed. Such challenges in mitigation approaches are featured for SRAMs (Static Random Access Memories), FFs (Flip-Flops), FPGAs (Field Programmable Gate Arrays) and computer systems as exemplified in the following articles: (i) Layout aware neutron-induced soft-error simulation and fault tolerant design techniques are introduced for 6T SRAMs. The PNP layout instead of conventional NPN layout is proposed and its robustness is demonstrated by using the MONTE CARLO simulator PHITS. (ii) RHBD (Radiation-Hardened By Design) FFs hardened by using specially designed redundant techniques are extensively evaluated. BCDMR (Bistable Cross-Coupled Dual Modular Redundancy) FFs is proposed in order to avoid MCU (Multi-Cell Upset) impacts on FF reliability. Its robustness is demonstrated thorough a set of neutron irradiation tests. (iii) CGRA (Coarse-Grained Reconfigurable Architecture) is proposed for an FPGA-chip-level tolerance. Prototype CGRA-FPGA chips are manufactured and their robustness is demonstrated under alpha particle/neutron irradiation tests. (iv) Simulation techniques for failures in heterogeneous computer system with memory hierarchy consisting of a register file, an L1 cache, an L2 cache and a main memory are also proposed in conjunction with masking effects of faults/errors.

Applications of Reconfigurable Processors as Embedded Automatons in the IoT Sensor Networks in Space

This chapter introduces the applications of the Flexible Reliability Reconfigurable Array (FRRA) processors, which is presented in Sect. 3.4, in a non-von Neumann architecture, and discusses its advantages when it is used in the Internet of Things (IoT) applications. FRRA is an embodiment of the concept of embedded automaton that we introduce as an essential element for building the IoT. We will start by looking at the role played by embedded system processors and point out that employing non-von Neumann architecture is inevitable (essential) to accomplish the speed/power performance required for embedded system applications. The major target application of embedded microprocessor is the IoT, and space-born sensor applications are quoted in this chapter as examples of the IoT. Space systems are somewhat special but are typical IoT applications which require dependability as an essential feature. Another important aspect of the embedded automaton based on the FRRA architecture is the contribution of behavioral synthesis technology. Practical application implementation on the reconfigurable processor is realized with the maturity of a high-level behavioral synthesis technology called CyberWorkBench (CWB).

Binary synthesis implementing external interrupt handler as independent module

This article presents a method of synthesizing hardware from a given executable binary code with an external interrupt handler, where the normal flow and the interrupt handling are executed by separate hardware modules. Our previous method synthesized the whole program into a single hardware module, in which register save/restore imposed limitations on the timing to start interrupt handling and also impaired efficiency of the synthesized hardware. By executing the two tasks on separate modules, register save/restore can be eliminated, which allows interrupt handler to start at arbitrary timing and reduces the response time and cost of the hardware. By allowing two processes to run in parallel, total execution time is also reduced. An experiment with a simple program has shown that the execution cycles and the delay were reduced by about 80% and 20%, respectively, as compared with MIPS CPU. A motor controller driven by periodical interrupts from a timer has been successfully synthesized from C and assembly programs, which runs more than 20 times faster than the MIPS CPU.

Distributed memory architecture for high-level synthesis of embedded controllers from Erlang

This paper presents a distributed memory architecture for dedicated hardware automatically synthesized from Erlang programs. Our team had developed a framework for generating embedded systems controllers whose behavior was specified by a subset of Erlang, where each process was mapped into hardware (a logic circuit) running independently of the circuits for the other processes. However, the resulting hardware was not of practical use because it shared a single main memory potentially accessed by all the circuits for the processes simultaneously. To address this issue, in this paper, the main memory is partitioned into banks so that each process can access its own memory independently of the other processes. In order to keep the interconnections for message passing to a practical size, a bus architecture is employed where send requests are arbitrated by an arbiter (logic circuit). In order to make the resulting hardware as small as possible, a garbage collection circuit is shared among the circuits for the processes also under the control of the arbiter. From a simple Erlang specification, Verilog HDL codes for necessary hardware to construct a system has been generated.

Novel processor architecture for onboard infrared sensors

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in a 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment.