Hiroshi Segawa

A chip set architecture for programmable real-time MPEG2 video encoder

This paper describes a chip set architecture for a programmable video encoder based on the MPEG2 main profile at main level (MP@ML). The chip set consists of a Controller-LSI (C-LSI), a macroblock level Pixel Processor-LSI (P-LSI) and a Motion Estimation-LSI (ME-LSI). The chip set combined with synchronous DRAMs (SDRAM) supports the whole layer processing including rate-control and realizes the real-time encoding for ITU-R-601 resolution video (720/spl times/480 pixels at 30 frame/s) with glueless logic. The exhaustive motion estimation capability is scalable up to +-63.5/+-15.5 in the horizontal/vertical directions. This chip set solution can realize a low cost MPEG2 video encoder system with excellent video quality on a small PC card.

A 50 ns video signal processor

A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538 k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0- mu m double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.<<ETX>>

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0- mu m CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment. >

Circuit device having a self-testing function and a testing method thereof

A semiconductor integrated circuit has a plurality of circuits (2 and 5) to be tested for verification of operation thereof and first, second and third scanning registers (1, 4 and 6) to be used for self-testing, and it further has a register (3) for delay. In operation, predetermined test data is inputted to each of the first and second scanning registers (1and 4) and then the first and second circuits (2 and 5) to be tested process those data simultaneously. Thus, testing time is saved. Although the time required for processing in the first circuit (2) to be tested is shorter than that in the second circuit (5) to be tested, the processed data can be obtained simutaneously by the delay function of the register (3).

A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores

A single chip MPEG2 video, audio, and system encoder for various applications such as PC authoring, DVD-recorder and digital TV has been described. It performs real-time 422@ML video encoding, Dolby Digital (AC-3)/MPEG1 audio encoding, and system encoding which multiplexes the video and audio streams and generates a transport stream or a program stream. The encoder LSI employs an advanced hybrid architecture with a 162-MHz media-processor and dedicated video processing hardware. This architecture not only realizes a complete encoder but also achieves the high flexibility required for improving picture quality. Dual motion estimation cores, fine ME for high search precision and coarse ME for a wide search range, are integrated for optimal motion vector search. The encoder LSI is implemented using 0.25 micron four-metal CMOS technology and integrates 11 million transistors in an area of 14.2/spl times/14.2 mm/sup 2/.

Vertically high-density interconnection for mobile application

Abstract There are several PWB technologies in the market that enables high density interconnection for product miniaturization, and this paper focuses on two HDI technologies, SSP and FVSS ® , and discuss the new PWB technologies and the reliability evaluation results for mobile applications. SSP is manufactured in simple lamination process using conventional FR4 materials, which enables future cost reduction and high reliability. FVSS contains filled buried via hole (BVH) and filled micro blind via (μvia) process. By combining the two process FVSS accomplishes high vertical design capability with Stacked μvia-on-μvia and stacked μvia-on-BVH designs. Key reliability requirements for final product quality is drop and temperature cycling reliability in board level in addition to evaluate PWB specific tests to compare performance of new materials used in PWB.