Atsuo Hanami

A chip set architecture for programmable real-time MPEG2 video encoder

This paper describes a chip set architecture for a programmable video encoder based on the MPEG2 main profile at main level (MP@ML). The chip set consists of a Controller-LSI (C-LSI), a macroblock level Pixel Processor-LSI (P-LSI) and a Motion Estimation-LSI (ME-LSI). The chip set combined with synchronous DRAMs (SDRAM) supports the whole layer processing including rate-control and realizes the real-time encoding for ITU-R-601 resolution video (720/spl times/480 pixels at 30 frame/s) with glueless logic. The exhaustive motion estimation capability is scalable up to +-63.5/+-15.5 in the horizontal/vertical directions. This chip set solution can realize a low cost MPEG2 video encoder system with excellent video quality on a small PC card.

A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.

A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications

A wide range motion estimation with exhaustive search is the best approach for high quality encoding applications. To perform the required computational power, a 165 GOPS (giga operations per second) exhaustive motion estimation processor ME3 has been developed. The ME3 is powerful enough to realize a range of -64/+63 pixels horizontally and -32/+31 pixels vertically with a single chip. A dual-array architecture supports not only high calculation power but also luminance and chrominance based search to increase picture quality. Also, the ME3 outputs extra vectors as candidates to enhance the picture quality. Using a multi-chip configuration, the exhaustive search range can be easily expanded to meet the requirements of MP@HL encoder. It is implemented using 0.35 /spl mu/m CMOS technology and contains 1.9 million transistors in an area of 8.5/spl times/8.5 mm/sup 2/.