Kazuya Konishi

Stacking fault expansion from basal plane dislocations converted into threading edge dislocations in 4H-SiC epilayers under high current stress

We evaluate the stacking faults (SFs) expansion from basal plane dislocations (BPDs) converted into threading edge dislocations (TEDs) under the current stress to the pn devices and analyzed the nucleation site of the SF by combined polishing, chemical etching in molten KOH, photoluminescence imaging, Focus ion beam, transmission electron microscopy, and Time-of-Flight secondary ion mass spectrometer techniques. It was found that the formation of SFs occurs upon the current stress levels of 400 A/cm2 where the diode area is not including BPDs in the drift layer after the high current stress, and the high current stress increases the SFs expansion density. It was also found the dependence of the junction temperature. The estimated activation energy for the expansion of SFs is Ea = 0.46 eV. The SF extends from the conversion point of the BPD into the TED within buffer layer. Even though BPDs converted into TEDs within the high doped buffer layer, SFs expand under high current stress.

Driving Force of Stacking Fault Expansion in 4H-SiC PN Diode by In Situ Electroluminescence Imaging

We evaluate the velocity of stacking faults (SFs) expansion under various current and temperature levels on the pn diodes by electroluminescence (EL) observation in situ. The driving force of the SFs expansion is analyzed on the basis of the experimental results. The velocity of the SFs expansion increases in proportional to the current density at the every junction temperature levels. The activation energy for the velocity of the SFs expansion is estimated.

Next generation 650V CSTBT TM with improved SOA fabricated by an advanced thin wafer technology

Using an advanced thin wafer technology, we have successfully fabricated the next generation 650V class IGBT with an improved SOA and maintaining the narrow distribution of the electrical characteristics for industrial applications. The applied techniques were the finer pattern transistor cell, the thin wafer process and the optimized back side doping concentration profiles. With the well organized back-side wafer process, the practically large chip has achieved without any sacrifice of the production yield. As a results, VCEsat-Eoff trade-off relationship and an Energy of Short Circuit by active Area (ESC/A) are improved in comparison with the conventional Punch Through (PT) structure.

Experimental demonstration of the active trench layout tuned 1200V CSTBT™ for lower dV/dt surge and turn-on switching loss

Optimization of a cell structure affecting gate capacitance must have an important role to upgrade usability of IGBT at high frequency operation. In this paper, we report an experimental study on the IGBT cell structures with various arrangements of active trenches connected to gate. Utilizing the advanced active trench layout with well-balanced capacitance realized to lower dV/dt surge and turn-on switching loss.

Effect of Stacking Faults in Triangular Defects on 4H-SiC Junction Barrier Schottky Diodes

The relationship between stacking faults and the position of the leakage current inside a triangular defect was analyzed. Triangular defects are categorized into two types on the basis of the current–voltage (I–V) characteristics. It was found that stacking faults (SFs) of the 3C structure inside a triangular defect increase leakage current at a reverse bias voltage as well as forward current at a low bias voltage, while SFs of the SF(4,2) structure inside a triangular defect do not lead to deterioration of device performance in this case.

Impact of Stripe Trench-Gate Structure for 4H-SiC Trench MOSFET with Bottom Oxide Protection Layer

An optimized layout for a trench-gate SiC-MOSFET with a self-aligned Bottom P-Well (BPW) was investigated for reduction of the specific on-resistance and switching loss. The static and dynamic characteristics of trench-gate MOSFETs with lattice and stripe in-plane structures were evaluated by varying the distance between neighboring BPWs (dBPWs). For the stripe structure, more significant improvements on the specific on-resistance (Ron,sp), gate-source threshold voltage (Vth) were achieved compared with the lattice structure, which was found to be due to the difference in the spread of the depletion layer and the channel planes in the device.