Tetsuro Nakasugi

Low-resistivity poly-metal gate electrode durable for high-temperature processing

A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100 nm)WN/sub x/(5 nm)/poly-Si structure. The W/WSiN/poly-Si structure was found to be thermally stable even after annealing at 800/spl deg/C. The sheet resistivity of the W(100 nm)/WN/sub x/(5 nm)/poly-Si(100 nm) structure is as low as 1.5 /spl Omega//spl par//spl square/ and independent of line-width from 0.52 /spl mu/m to 0.12 /spl mu/m. The sheet resistivity of this layer structure is 40% lower than that of the W(100 nm)/TiN(5 nm)/poly-Si structure. In addition, an equivalent circuit simulation showed that the measured contact resistivity of W and poly-Si in the W/WSiN/poly-Si system did not affect the gate RC delay time. Finally, a process integration of the poly-metal gate electrode is discussed. A SiN capped poly-metal structure was demonstrated.

Nanoimprint lithography and future patterning for semiconductor devices

Nanoimprint lithography (NIL) has the potential capability of high resolution with critical dimension uniformity that is suited for patterning shrinkage, as well as providing a low cost advantage. However, the defectivity of NIL is an impediment to the practical use of the technology in semiconductor manufacturing. We have evaluated defect levels of NIL and have classified defectivity into three categories; nonfill defects, template defects, and plug defects. New materials for both the template and resist processes reduce these defects to practical levels. Electric yields of NIL are also discussed.

Nanoimprint Lithography for Semiconductor Devices and Future Patterning Innovation

Nanoimprint lithography (NIL) has been expected as a low cost lithography solution as well as pattern shrinking capability with superior Critical Dimension (CD) uniformity for several years. However, NIL had been considered having difficulty to be established as mass-production technology, unless the challenge of defectivity control is overcome. The defects of NIL are classified into the non-fill defect, the template defect, and the plug defect. In order to reduce these defects, establishment of the technical infrastructures is important with the innovations of equipment, material, and template technologies. Recently, the investment to lithography becomes heavier burden for a semiconductor device maker, as lithography technology has been more difficult for further pattern shrinking. Therefore, expectation of NIL realization has emerged again. This paper describes current NIL technical status and refers to a future NIL patterning innovation such as a desktop lithography.

Aberration budget in extreme ultraviolet lithography

It seems that the actual EUV lithography tools will have aberrations around ten times larger than those of the latest ArF lithography tools in wavelength normalized rms. We calculated the influence of aberrations on the size error and pattern shift error using Zernike sensitivity analysis. Mask-induced aberration restricts the specification of aberration. Without periodic additional pattern, the aberration to form 22 nm dual-gate patterns was below 8 mλ rms. Arranging the periodic additional pattern relaxed the aberration tolerance. With periodic additional pattern, the aberration to form 22 nm patterns was below 37 mλ rms. It is important to make pattern periodicity for the relaxation of the aberration specification.

Alignment system using voltage contrast images for low-energy electron-beam lithography

We have proposed an alignment system for low-energy electron-beam lithography. The proposed alignment system is based on the following unique concepts: (1) an alignment mark is detected using voltage contrast images caused by charging, and (2) to improve the alignment accuracy of global alignment, the alignment accuracy can be inspected before the pattern exposure without any loss of time. In order to verify these concepts, we performed a series of experiments. Using an electron beam of a few keV, we detected a mark buried by thick insulator films; even if direct access to the marks by the primary beam is prevented, the mark detection is possible. Also, we confirmed that the simultaneous observation of exposure patterns and alignment mark is possible using the voltage contrast images caused by charging: the inspection is possible for the exposure status without resist development.

Maskless lithography: a low-energy electron-beam direct writing system with a common CP aperture and the recent progress

In order to realize SoC (System on a Chip) fabrication at low cost with quick-TAT (Turn-Around-Time) we have proposed a maskless lithography (ML2) strategy, a low-energy electron-beam direct writing (LEEBDW) system with a common character projection (CP) aperture. This paper presents a status report on our proof-of-concept (POC) system. We have developed a compact EB column consisting small electrostatic lenses and deflectors. The experimental results for our POC system indicated that the patterns corresponding to 50nm-node logic devices can be obtained with CP exposure at the incident energy of 5 keV. The technique to reduce the raw process time using a SEM function of LEEBDW system is also reported.

Edge Roughness Study of Chemically Amplified Resist in Low-Energy Electron-Beam Lithography Using Computer Simulation

We investigated the line edge roughness (LER) of chemically amplified resist (CAR) in the high-sensitivity resist process in low-energy electron beam lithography (LEEBL). We have confirmed that a sub-100 nm pattern having a small line edge roughness could be obtained at the exposure dose below sub-1 µC/cm2 for LEEBL. In order to explain the experimental results, we have proposed a resist exposure model, considering the generation yield and diffusion of secondary electrons (SEs). Based on the proposed model, we analyzed the LER for LEEBL using a simulation. When the beam blur and the acceptable LER were 30 nm (σ) and 2 nm (σ), the acceptable exposure doses for 2–5 keV and 50 keV were 0.3 µC/cm2 and 2.5 µC/cm2, respectively. This means that a high-sensitivity CAR process at the exposure dose below 0.5 µC/cm2 can be achieved in LEEBL.

New registration technique using voltage-contrast images for low-energy electron-beam lithography

We have developed a new registration technique for low energy electron beam lithography. A notable feature of this technique is the use of voltage contrast images caused by charging at the resist surface. Using the electron beam of incident energy range of 1keV to 4.5keV, we detected the mark buried by thick insulator films; even if direct access tot he marks by the primary beam is prevented, the mark detection is possible. The detection time is a few milliseconds, and it is sufficiently fast. We confirmed that this technique is available for various layers of DRAM. Also the possible mechanism that may explain the voltage contrast image caused by negative charging is discussed.

Proximity Effect Correction For Electron Beam Lithography: Highly Accurate Correction Method

A new formula for proximity effect correction is discussed. The formula is represented by a series expansion. When infinite terms are used, the formula gives accurate optimum correction doses. The correction accuracy of the new formula is evaluated for the worst case scenario and compared with the conventional formula. It is shown that (1) the new formula suppresses correction errors to less than 0.5% for the deposited energy and (2) dimensional errors are less than 4 nm, even if only the first 3 terms are calculated for critical patterns. By using the new formula, the proximity effect correction can be carried out with sufficient accuracy, even for making reticles of 1 Gbit or higher-capacity DRAMs.

Sub-100 nm pattern formation by roll-to-roll nanoimprint

Technologies for pattern fabrication on a flexible substrate are being developed for various flexible devices. A patterning technique for a smaller pattern of the order of sub-100 nm will be needed in the near future. Roll-to-roll Nano-Imprint Lithography (RtR-NIL) is promising candidate for extremely low-cost fabrication of large-area devices in large volumes. We have tried to transfer sub-100 nm patterns, especially sub-30 nm patterns, onto ultraviolet (UV) curable resin on film substrate by RtR-NIL. We demonstrate a 24 nm pattern on a film substrate by RtR-NIL and the methods potential for sub-100 nm patterning.