Kei Kobayashi

Noncontact-mode scanning capacitance force microscopy towards quantitative two-dimensional carrier profiling on semiconductor devices

Scanning capacitance force microscopy (SCFM) is a promising tool for investigation of two-dimensional carrier density distribution on semiconducting devices. Its sensitivity is strongly dependent on the Q factor of the mechanical resonance mode of the cantilever. Therefore, measurement in vacuum is more appropriate for increasing the sensitivity. In this letter, the authors describe noncontact-mode (NC) SCFM which is combined with the frequency modulation detection method and its signal characteristics. The authors derived a quasiquantitative calibration curve which correlates to the amplitude signal in NC-SCFM to the dopant density. Using the calibration curve, the authors obtained a quasiquantitative two-dimensional dopant density distribution map on a cross-sectional transistor device.

NIL defect performance toward high volume mass production

A low cost alternative lithographic technology is desired to meet with the decreasing feature size of semiconductor devices. Nanoimprint lithography (NIL) is one of the candidates for alternative lithographic technologies. NIL has advantages such as good resolution, critical dimension (CD) uniformity and smaller line edge roughness (LER). 4 On the other hand, NIL involves some risks. Defectivity is the most critical issue in NIL. The progress in the defect reduction on templates shows great improvement recently. In other words, the defect reduction of the NIIL process is a key to apply NIL to mass production. In this paper, we describe the evaluation results of the defect performance of NIL using an up-to-date tool, Canon FPA-1100 NZ2, and discuss the future potential of NIL in terms of defectivity. The impact of various kinds defects, such as the non-filling defect, plug defect, line collapse, and defects on replica templates are discussed. We found that non-fill defects under the resist pattern cause line collapse. It is important to prevent line collapse. From these analyses based on actual NIL defect data on long-run stability, we will show the way to reduce defects and the possibility of NIL in device high volume mass production. For the past one year, we have been are collaborating with SK Hynix to bring this promising technology into mainstream manufacturing. This work is the result of this collaboration.

Study of nanoimprint lithography (NIL) for HVM of memory devices

A low cost alternative lithographic technology is desired to meet the decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the candidates for alternative lithographic technologies.[1][2][3] NIL has such advantages as good resolution, critical dimension (CD) uniformity and low line edge roughness (LER). On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the HVM, it is necessary to overcome these three challenges simultaneously.[4]-[12] In our previous study, we have reported a dramatic improvement in NIL process defectivity on a pilot line tool, FPA-1100 NZ2. We have described that the NIL process for 2x nm half pitch is getting closer to the target of HVM.[12] In this study, we report the recent evaluation of the NIL process performance to judge the applicability of NIL to memory device fabrications. In detail, the CD uniformity and LER are found to be less than 2nm. The overlay accuracy of the test device is less than 7nm. A defectivity level of below 1pcs./cm2 has been achieved at a throughput of 15 wafers per hour.

Material development for high-throughput nanoimprint lithography

Nanoimprint lithography (NIL) is a candidate of alternative lithographic technology for memory devices. We are developing NIL technology and challenging critical issues such as defectivity, overlay, and throughput . NIL material is a key factor to support the robust patterning process. Especially, resist material can play an important role in addressing the issue of the total throughput performance. The aim of this research is to clarify key factors of resist property which can reduce resist filling time and template separation time . The liquid resist is filled in the relief patterns on a quartz template surface and subsequently cured under UV radiation. The filling time is a bottleneck of NILthroughput. We have clarified that the air trapping in the liquid resist is critical. Based on theoretical study, we have identified key factors of NIL-resist property. These results have provided a deeper insight into resist material for high throughput NIL.

Improvement of nano-imprint lithography performance for device fabrication

A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates.[1][2][3] NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. NIL is a simple technology and is capable of forming critical patterns easily. On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the High Volume Manufacturing (HVM), it is necessary to overcome these three challenges simultaneously.[4]-[10] In our previous study, we have reported improvement in NIL overlay, defectivity and throughput by the optimization of resist process on a pilot line tool, FPA-1200 NZ2C. In this study, we report recent evaluation of the NIL performance to judge its applicability in semiconductor device HVM. We have described that the NIL is getting closer to the target of HVM for 2x nm half pitch.[8]Defectivity level below 1pcs/cm2 has been achieved for the 2x nm half pitch L/S. The overlay accuracy of the test device is being improved down to 6nm or lower by introducing high order distortion correction.

The opportunity and challenge of spin coat based nanoimprint lithography

Since multi patterning with spacer was introduced in NAND flash memory1, multi patterning with spacer has been a promising solution to overcome the resolution limit. However, the increase in process cost of multi patterning with spacer must be a serious burden to device manufacturers as half pitch of patterns gets smaller.2, 3 Even though Nano Imprint Lithography (NIL) has been considered as one of strong candidates to avoid cost issue of multi patterning with spacer, there are still negative viewpoints; template damage induced from particles between template and wafer, overlay degradation induced from shear force between template and wafer, and throughput loss induced from dispensing and spreading resist droplet. Jet and Flash Imprint Lithography (J-FIL4, 5, 6) has contributed to throughput improvement, but still has these above problems. J-FIL consists of 5 steps; dispense of resist droplets on wafer, imprinting template on wafer, filling the gap between template and wafer with resist, UV curing, and separation of template from wafer. If dispensing resist droplets by inkjet is replaced with coating resist at spin coater, additional progress in NIL can be achieved. Template damage from particle can be suppressed by thick resist which is spin-coated at spin coater and covers most of particles on wafer, shear force between template and wafer can be minimized with thick resist, and finally additional throughput enhancement can be achieved by skipping dispense of resist droplets on wafer. On the other hand, spin-coat-based NIL has side effect such as pattern collapse which comes from high separation energy of resist. It is expected that pattern collapse can be improved by the development of resist with low separation energy.