Takuya Kono

Sub-100 nm pattern formation by roll-to-roll nanoimprint

Technologies for pattern fabrication on a flexible substrate are being developed for various flexible devices. A patterning technique for a smaller pattern of the order of sub-100 nm will be needed in the near future. Roll-to-roll Nano-Imprint Lithography (RtR-NIL) is promising candidate for extremely low-cost fabrication of large-area devices in large volumes. We have tried to transfer sub-100 nm patterns, especially sub-30 nm patterns, onto ultraviolet (UV) curable resin on film substrate by RtR-NIL. We demonstrate a 24 nm pattern on a film substrate by RtR-NIL and the methods potential for sub-100 nm patterning.

Alignment mark signal simulation system for the optimum mark feature selection

Recently, requirements concerning overlay accuracy have become much more restrictive. For the accurate overlay, signal intensity and wave form from the topographical alignment mark have been examined by signal simulation. However, even if the results were in good agreement with actual signal profiles, it would be difficult to select particular alignment marks at each mask level by the signal simulation. Therefore, many mark candidates are left in the kerf area after mass production. To facilitate the selection, we propose a mark TCAD system. It is a useful system for the mark selection with the signal simulation performed in advance. In our system, the alignment mark signal can be easily simulated after input of some process material parameters and process of record (POR). The POR is read into the system and a process simulator makes stacked films on a wafer. Topographical marks are simulated from the stacked films and the resist pattern. The topographical marks are illuminated and reflected beams are produced. Imaging of the reflected beams through inspection optics is simulated. In addition, we show two applications. This system is not only for predicting and showing a signal wave form, but is also helpful for finding the optimum marks.

Patterning strategy and performance of 1.3NA tool for 32nm node lithography

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

NIL defect performance toward high volume mass production

A low cost alternative lithographic technology is desired to meet with the decreasing feature size of semiconductor devices. Nanoimprint lithography (NIL) is one of the candidates for alternative lithographic technologies. NIL has advantages such as good resolution, critical dimension (CD) uniformity and smaller line edge roughness (LER). 4 On the other hand, NIL involves some risks. Defectivity is the most critical issue in NIL. The progress in the defect reduction on templates shows great improvement recently. In other words, the defect reduction of the NIIL process is a key to apply NIL to mass production. In this paper, we describe the evaluation results of the defect performance of NIL using an up-to-date tool, Canon FPA-1100 NZ2, and discuss the future potential of NIL in terms of defectivity. The impact of various kinds defects, such as the non-filling defect, plug defect, line collapse, and defects on replica templates are discussed. We found that non-fill defects under the resist pattern cause line collapse. It is important to prevent line collapse. From these analyses based on actual NIL defect data on long-run stability, we will show the way to reduce defects and the possibility of NIL in device high volume mass production. For the past one year, we have been are collaborating with SK Hynix to bring this promising technology into mainstream manufacturing. This work is the result of this collaboration.

Overlay improvement in nanoimprint lithography for 1×-nm patterning

Nanoimprint lithography (NIL) is becoming a promising technique for fine-patterning with a lower cost than other lithography techniques. High overlay accuracy is one of the issues in NIL. Using die-by-die alignment with moire fringe detection, an NIL alignment measurement accuracy below 1 nm and an overlay accuracy below 5 nm have been reported. On the other hand, the requirement for overlay in 2020 is estimated to be 3–4 nm for dynamic random access memory, flash and logic devices. In order to make the overlay accuracy requirement qualify from the semiconductor industry, a lot of technology enhancements, such as the improvement of overlay control accuracy for NIL-tools, image placement accuracy improvement for NIL templates, mix and match technique of NIL, and other lithography tools such as immersion exposure ones, are needed. In this paper, the authors describe the evaluation of the NIL overlay performance using up-to-date NIL tools, and discuss the potentials of NIL overlay in the future. Alignment ac...

Solutions with precise prediction for thermal aberration error in low-k1 immersion lithography

Thermal aberration becomes a serious problem in the production of semiconductors for which low-k1 immersion lithography with a strong off-axis illumination, such as dipole setting, is used. The illumination setting localizes energy of the light in the projection lens, bringing about localized temperature rise. The temperature change varies lens refractive index and thus generates aberrations. The phenomenon is called thermal aberration. For realizing manufacturability of fine patterns with high productivity, thermal aberration control is important. Since heating areas in the projection lens are determined by source shape and distribution of diffracted light by a mask, the diffracted pupilgram convolving illumination source shape with diffraction distribution can be calculated using mask layout data for the thermal aberration prediction. Thermal aberration is calculated as a function of accumulated irradiation power. We have evaluated the thermal aberration computational prediction and control technology “Thermal Aberration Optimizer” (ThAO) on a Nikon immersion system. The thermal aberration prediction consists of two steps. The first step is prediction of the diffraction map on the projection pupil. The second step is computing thermal aberration from the diffraction map using a lens thermal model and an aberration correction function. We performed a verification test for ThAO using a mask of 1x-nm memory and strong off-axis illumination. We clarified the current performance of thermal aberration prediction, and also confirmed that the impacts of thermal aberration of NSR-S621D on CD and overlay for our 1x-nm memory pattern are very small. Accurate thermal aberration prediction with ThAO will enable thermal aberration risk-free lithography for semiconductor chip production.

Integration of a new alignment sensor for advanced technology nodes

In this paper alignment and overlay results of the advanced technology nodes are presented. These results were obtained on specially generated wafers as well as on regular manufacturing-type wafers. For this purpose, a new alignment sensor was integrated and evaluated in three generations of lithography tools, placed in R&D and mass manufacturing facilities. The capability of the sensor to align on marks with varying layout was evaluated. Long term overlay stability less than 11 nm was obtained on two different mark types: a standard ASML calibration mark and a flexible Toshiba mark design. The ability to align on low-contrast marks was validated by a dedicated experiment: typical alignment repeatability values of ~1 nm (3sigma) on shallow etch depth mark features of 25 nm are obtained for various mark designs, including flexible pitch alignment marks. From these results, design directions for improved mark detect ability were defined. The jointly developed mark designs were validated for their alignment robustness by an evaluation of manufacturing wafer alignment performance. On-product overlay results on manufacturing wafers were measured for three different process layers of the current technology node. The used alignment strategies were based on new mark capture and fine wafer alignment mark designs, thereby making optimal use of the mark design flexibility potential of the alignment sensor. Typical on-product overlay values obtained were less than 17 nm for the Active Area process layer, less than 12 nm for the Gate Conductor process layer, and less than 19 nm for the Metal-1 process layer; after applying batch corrections, as determined on a set of 2 send-ahead wafers. All results are based on full batch readout on an offline metrology tool. By applying optimal batch process corrections for linear terms, typical overlay values range between 10-14 nm, depending on the layer measured. Finally the sensors infrared wavelengths were used to demonstrate a robust alignment solution for wafers containing a semi-transparent hard-mask layer.

Basic studies of overlay performance on immersion lithography tool

Immersion lithography with ArF light and Ultra Pure Water (UPW) is the most promising technology for semiconductor manufacturing with 65 nm hp design and below. Since Nikon completed the first full-field immersion scanner, the Engineering Evaluation Tool (EET, NA=0.85) at the end of 2004, Toshiba and Nikon have investigated overlay accuracy with the EET which uses the local fill nozzle. EET successfully demonstrated immersion tools are comparable in single machine overlay accuracy to dry tools, and immersion-dry matching has the same level overlay matching accuracy as dry-dry matching. EET also made it clear that overlay accuracy is independent of scanning speed, and both solvent-soluble topcoats, as well as developer-soluble topcoats can be used without degradation of overlay accuracy. We investigated the impact of the thermal environment on overlay accuracy also, assuming that a key technology of overlay with immersion tools must achieve thermal stabilities similar to dry tools. It was found that the temperature of supply water and loading wafer are stable enough to keep the overlay accuracy good. As for evaporation heat, water droplets on the backside of the wafer lead to overlay degradation. We have decided to equip the wafer holder of S609B, the first immersion production model, with an advanced watertight structure.

Design for nanoimprint lithography: total layout refinement utilizing NIL process simulation

Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.

Patterning performance of hyper NA immersion lithography for 32nm node logic process

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.