Masayuki Hatano

Fabrication of Silicon-on-Nothing Structure by Substrate Engineering Using the Empty-Space-in-Silicon Formation Technique

A practical method for the fabrication of a silicon on nothing (SON) structure with the desired size and shape has been developed by using the empty-space-in-silicon (ESS) formation technique. It was found that the SON structure could be precisely controlled by the initial shape and layout of the trenches. The size of ESS is determined by the size of the initial trench. The desired shapes of ESS, such as spherical, pipe-shaped and plate-shaped, can be fabricated by changing the arrangement of the initial trenches. The fabricated SON region over ESS has excellent crystallinity adoptable for ultra-large-scale integrated circuit (ULSI) applications. The SON structure would be a promising substrate structure for various manufacturing technologies, such as the micro-electro-mechanical system (MEMS), photonic crystals and waveguides.

NIL defect performance toward high volume mass production

A low cost alternative lithographic technology is desired to meet with the decreasing feature size of semiconductor devices. Nanoimprint lithography (NIL) is one of the candidates for alternative lithographic technologies. NIL has advantages such as good resolution, critical dimension (CD) uniformity and smaller line edge roughness (LER). 4 On the other hand, NIL involves some risks. Defectivity is the most critical issue in NIL. The progress in the defect reduction on templates shows great improvement recently. In other words, the defect reduction of the NIIL process is a key to apply NIL to mass production. In this paper, we describe the evaluation results of the defect performance of NIL using an up-to-date tool, Canon FPA-1100 NZ2, and discuss the future potential of NIL in terms of defectivity. The impact of various kinds defects, such as the non-filling defect, plug defect, line collapse, and defects on replica templates are discussed. We found that non-fill defects under the resist pattern cause line collapse. It is important to prevent line collapse. From these analyses based on actual NIL defect data on long-run stability, we will show the way to reduce defects and the possibility of NIL in device high volume mass production. For the past one year, we have been are collaborating with SK Hynix to bring this promising technology into mainstream manufacturing. This work is the result of this collaboration.

Overlay improvement in nanoimprint lithography for 1×-nm patterning

Nanoimprint lithography (NIL) is becoming a promising technique for fine-patterning with a lower cost than other lithography techniques. High overlay accuracy is one of the issues in NIL. Using die-by-die alignment with moire fringe detection, an NIL alignment measurement accuracy below 1 nm and an overlay accuracy below 5 nm have been reported. On the other hand, the requirement for overlay in 2020 is estimated to be 3–4 nm for dynamic random access memory, flash and logic devices. In order to make the overlay accuracy requirement qualify from the semiconductor industry, a lot of technology enhancements, such as the improvement of overlay control accuracy for NIL-tools, image placement accuracy improvement for NIL templates, mix and match technique of NIL, and other lithography tools such as immersion exposure ones, are needed. In this paper, the authors describe the evaluation of the NIL overlay performance using up-to-date NIL tools, and discuss the potentials of NIL overlay in the future. Alignment ac...

Design for nanoimprint lithography: total layout refinement utilizing NIL process simulation

Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.

Study of nanoimprint lithography (NIL) for HVM of memory devices

A low cost alternative lithographic technology is desired to meet the decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the candidates for alternative lithographic technologies.[1][2][3] NIL has such advantages as good resolution, critical dimension (CD) uniformity and low line edge roughness (LER). On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the HVM, it is necessary to overcome these three challenges simultaneously.[4]-[12] In our previous study, we have reported a dramatic improvement in NIL process defectivity on a pilot line tool, FPA-1100 NZ2. We have described that the NIL process for 2x nm half pitch is getting closer to the target of HVM.[12] In this study, we report the recent evaluation of the NIL process performance to judge the applicability of NIL to memory device fabrications. In detail, the CD uniformity and LER are found to be less than 2nm. The overlay accuracy of the test device is less than 7nm. A defectivity level of below 1pcs./cm2 has been achieved at a throughput of 15 wafers per hour.

Material development for high-throughput nanoimprint lithography

Nanoimprint lithography (NIL) is a candidate of alternative lithographic technology for memory devices. We are developing NIL technology and challenging critical issues such as defectivity, overlay, and throughput . NIL material is a key factor to support the robust patterning process. Especially, resist material can play an important role in addressing the issue of the total throughput performance. The aim of this research is to clarify key factors of resist property which can reduce resist filling time and template separation time . The liquid resist is filled in the relief patterns on a quartz template surface and subsequently cured under UV radiation. The filling time is a bottleneck of NILthroughput. We have clarified that the air trapping in the liquid resist is critical. Based on theoretical study, we have identified key factors of NIL-resist property. These results have provided a deeper insight into resist material for high throughput NIL.

Improvement of nano-imprint lithography performance for device fabrication

A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates.[1][2][3] NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. NIL is a simple technology and is capable of forming critical patterns easily. On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the High Volume Manufacturing (HVM), it is necessary to overcome these three challenges simultaneously.[4]-[10] In our previous study, we have reported improvement in NIL overlay, defectivity and throughput by the optimization of resist process on a pilot line tool, FPA-1200 NZ2C. In this study, we report recent evaluation of the NIL performance to judge its applicability in semiconductor device HVM. We have described that the NIL is getting closer to the target of HVM for 2x nm half pitch.[8]Defectivity level below 1pcs/cm2 has been achieved for the 2x nm half pitch L/S. The overlay accuracy of the test device is being improved down to 6nm or lower by introducing high order distortion correction.

The prospects of design for roll to roll lithography: layout refinement utilizing process simulation

Directed self-assembly (DSA) of block copolymers (BCPs) is a promising method for producing the sub-20nm features required for future semiconductor device scaling, but many questions still surround the issue of defect levels in DSA processes. Knowledge of the free energy associated with a defect is critical to estimating the limiting equilibrium defect density that may be achievable in such a process. In this work, a coarse grained molecular dynamics (MD) model is used to study the free energy of a dislocation pair defect via thermodynamic integration. MD models with realistic potentials allow for more accurate simulations of the inherent polymer behavior without the need to guess modes of molecular movement and without oversimplifying atomic interactions. The free energy of such a defect as a function of the Flory- Huggins parameter (χ) and the total degree of polymerization (N) for the block copolymer is also calculated. It is found that high pitch multiplying underlayers do not show significant decreases in defect free energy relative to a simple pitch doubling underlayer. It is also found that χN is not the best descriptor for correlating defect free energy since simultaneous variation in chain length (N) and χ value while maintaining a constant χN product produces significantly different defect free energies. Instead, the defect free energy seems to be directly correlated to the χ value of the diblock copolymer used. This means that as higher χ systems are produced and utilized for DSA, the limiting defect level will likely decrease even though DSA processes may still operate at similar χN values to achieve ever smaller feature sizes.

Double Gate MOSFET by ESS (Empty Space in Silicon) Architecture

Double gate (DG) MOSFET employing ESS (Empty Space in Silicon) architecture exhibited remarkable device characteristics. Significant performance gain was clearly observed comparing to a planer bulk device. This advantage is mainly due to the steep sub-threshold characteristic which is the typical double gate feature. The ESS double gate architecture is fully compatible with current conventional bulk CMOS process. This typical feature could make double gate FET into realistic candidate of next high performance device. Introduction FD/DG/GAA-SOI has been discussed as a promising structure for future scaling devices because of the high SCE and DIBL immunity. However, complicated integration scheme will be needed to realize such kind of devices. On the other hand, we had developed the new technique to fabricate SON (Silicon on Nothing) structure on bulk substrate, named ESS technique. The ESS technique has several advantages; (1) Partial SOI (SON) on bulk substrate: The merit of SOI structure can be utilized on bulk wafer. This is appropriate for System on a Chip (SoC) applications. (2) Simple process: The ESS process needs only the trench fabrication and high temperature annealing. This will produce significant process cost reduction comparing to the use of SOI wafer. (3) Low self-heating: The ESS structure is made at part of active area region. Thus, thermal flux can easily flow into the Si substrate. (4) Free layout: ESS with the arbitrary size and shape can be formed by controlling the initial trench size and layout. In this paper, distinguished DG FET characteristics will be demonstrated with practical ESS architecture. DG-ESS FET Process A simple process sequence of the DG-ESS FET is shown in Fig. 1. First, high aspect ratio trenches were formed at surface of Si wafer. After that, ESS was formed by the trench transformation on high temperature hydrogen annealing. Next, SON thickness was thinned by CMP and oxidation process. Then, flat device surface over the ESS was obtained. STI pattern was aligned with ESS pattern. Conventional CMOS process could be applied after STI process. In this study , HDP-USG (anisotropic deposition property) was used for filling the STI. Thus, the ESS was not filled at STI formation step and a seam was created beside the ESS. As a result, the ESS was filled by polysilicon as a bottom gate electrode at the same time of top gate electrode deposition. The surrounding gate structure was made with this buried polysilicon. Figure 2 shows the schematic layout of the DG-ESS FET. Pipe-shaped ESS is formed under the top gate and extends to the STI region. Figures 3 and 4 show the TEM image of the A-A’ and B-B’ cross section of the fabricated DG-ESS FET, respectively. No defect was observed at the channel region and around ESS structure. Also it was confirmed that the thin flat Si layer surrounded by the poly silicon gate could successfully be obtained. In this structure, there is no need to make a contact to bottom gate electrode. The bottom surface of active Si layer was atomically flat due to surface migration. Thus, thickness of active Si layer became quite uniform as can be seen in fig. 4. Device Characteristics and Discussions Electrical results of DG-ESS FET were verified comparing to conventional bulk MOSFET, which were fabricated on the same wafer. The size of ESS and the thickness of the active Si layer should be well controlled to enjoy the merits of DG structure. Figure 5 shows the dependence of threshold voltage on substrate voltage at several gate lengths. The body effect coefficient of DG-ESS FET is varying with the change of gate length for a given ESS size. At the short channel region, where the gate length is shorter than the size of ESS, channel region is electrically isolated from the substrate. This device is same as floating body double gate structure. Figure 6 shows ideal subthreshold property at the shortest gate length which is around 0.2μm. On the other hand, in case that gate length is 1.0μm, which is larger than the ESS size, there is no difference in device characteristics at all regardless of ESS. As shown in Figs. 5 and 6, gate length has to be set shorter than ESS size to obtain the merit of floating body double gate device. Typical Id-Vg and Id-Vd characteristics of DG-ESS FET are shown in figs. 7 and 8, respectively. Steep subthreshold characteristics and higher drive current were observed. Drain current enhancement of DG-ESS FET was successfully achieved by 75% for NMOS and 97% for PMOS comparing to bulk FET which has same device width. On the other hand, the series resistance in the extension region could become important when the gate length becomes much shorter than the ESS size. However, the size of ESS is well controllable for each gate length. Finally, self-heating effect, which is one of critical issues of SOI device, was simulated using SON FET structure. The lattice temperature distribution due to self-heating was simulated as shown in Fig. 9 for conventional SOI FET(left) and SON FET(right). The better heat dissipation was clearly confirmed on SON FET since there is no insulator under source and drain region. DG-ESS FET shows more better heat dissipation than SON FET because SON region is filled with silicon, which has 100x lower thermal resistance compare to buried oxide. Conclusions DG-ESS FET was successfully realized by using ESS technique. DG-ESS FET shows the high drivability and good subthreshold property. Simple process sequence for making DG device has been demonstrated, which is compatible with conventional CMOS process. As a result, this novel scheme can fabricate both double gate and conventional device on the same wafer without any performance degradation. These results suggest that DG devices using ESS architecture is appropriate for SoC applications, due to the merit that DG structure can be fabricated partially on bulk substrate. References 1) J. P. Colinge et al., SSDM Tech. Dig., p.238, 2001. 2) D. Hisamoto, IEDM Tech. Dig., p.429, 2001. 3) S. Monfray et al., VLSI Tech. Dig., p.108, 2002. 4) T. Sato et al., IEDM Tech. Dig., p.517, 1999. 5) I. Mizushima et al., Appl. Phys. Lett., 77, p.3290, 2000. 6) T. Sato et al., IEDM Tech. Dig., p.809, 2001. Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, Tokyo, 2003, 762 B-10-6L pp. 762-763