Hirokazu Honda

Signal Integrity and Power Integrity Properties of FCBGA Based on Ultra-Thin, High-Density Packaging Substrate

We developed an ultra-thin high-density packaging substrate, called an MLTS (multi-layer thin substrate), that consists only of build-up layers without a core laminate. We evaluated the signal integrity and power integrity properties of a flip-chip ball grid array (FCBGA) based on the MLTS, along with those of an identically functioning FCBGA based on conventional build-up printed wiring board (PWB). Our signal-integrity simulation clearly showed that the return loss (S11) of the MLTS was 6 dB smaller than that of the PWB in the frequency range from 1 to 10 GHz. In our power-integrity simulation, the noise transmitted inside the MLTS was 13 dB smaller than that inside the PWB at 10 GHz. These results indicate that the MLTS has considerable advantages over a conventional build-up PWB, especially for operation in the GHz range.

High-performance FCBGA based on multi-layer thin-substrate packaging technology

Abstract We developed a new concept flip-chip ball grid array (FCBGA) based on multi-layer thin-substrate (MLTS) packaging technology in order to meet the strong demand for high-density, high-performance, and low-cost LSI packages. The most important feature of MLTS packaging is that, only a high-density and high-performance MLTS remains by removing the metal plate after mounting an LSI chip. The MLTS packaging offers the advantages of (1) good registration accuracy, which makes higher-density and finer-pitch pattering possible; (2) an ideal multi-layer structure that is highly suitable for high-speed and high-frequency applications; (3) excellent flip-chip mounting reliability, which makes higher-pin-count and finer-pitch area array flip-chip interconnection possible; (4) excellent reliability, supported by use of high T g (glass transition temperature) resin; and (5) a cost-effective design achieved as a result of fewer layers fabricated with fine-pitch patterning. We successfully produced a high-performance FCBGA prototype based on our MLTS packaging technology. The prototype comprises an LSI chip connected to approximately 2500 bonding pads arranged in 240 μm pitch area array, and 1296 I/O pads for BGA. The prototype FCBGA’s excellent long-term reliability was demonstrated through a series of tests conducted on it.

A 5-μm-width multi-layer wafer-level Cu wiring technology with resin CMP for highly-reliable FCBGA

A three-layer wafer-level copper wiring technology adaptable to a large flip-chip ball-grid array (FCBGA) package is successfully developed. This technology features fine 10-mum-pitch copper wiring, with 5-mum thickness, fabricated by a semi-additive process that employs a resin CMP process making each layer flat. A non-photosensitive polyimide is adopted as an insulating material, because it has superior mechanical properties compared to epoxy resin. A prototype chip with a size of 17.3times17.3-mm and three-layer copper wiring is fabricated and packaged into a 50times50-mm FCBGA. This prototype package demonstrates excellent long-term reliability in high-temperature and humidity bias tests (HHBT) and chip-level and package-level thermal-cycle tests (TCTs). Our technology is suitable for future low-cost ULSI wiring and long-distance data-transmission lines in a system-in-package (SiP).

Helical Wiring Type Stress Relaxation Structures for LSI Packages

Thermal stress, which is caused by the difference in thermal expansion coefficients of different materials, is a serious problem for large scale integrated (LSI) circuit packaging. The stress causes damage to LSI devices, especially those that have low-k materials in their LSI layer, and packaging substrates. We have developed a helical-micro-spring (HMS) to reduce damage due to thermal stress. The spring has a helical wiring structure that relieves any thermal stress. We have fabricated the HMS using a negative-type photopolymers or a positive-type photopolymer as dielectric layers. We have also simulated the springs mechanical and electrical properties and compared the properties with other stress relaxation structure.