Katsumi Kikuchi

A novel "SMAFTI" package for inter-chip wide-band data transfer

A package structure with inter-chip connection is proposed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a fine-wiring pattern and ultra-fine-pitch through vias. The FTI is formed on a silicon wafer using a photolithography process to realize fine vias and fine wiring patterns. This structure enables over a thousand inter-chip connections and a high pin count in the logic device. This paper describes the concept, structure, process, and experimental results of prototypes of this package called SMAFTI (SMArt chip connection with FeedThrough Interposer). This paper also reports the results of intermetallic compound analysis and thermal cycle test (TCT) that were performed to confirm the fundamental reliability of this novel inter-chip connection structure

New high-density multilayer technology on PCB

Demand has recently increased for very high-density packaging substrates for high-pin-count area array chips. Our new high-density multilayer technology on printed circuit board (PCB), named deposited substrate on laminate (DSOL) satisfies this demand. An important feature of the DSOL is dielectric fabrication, which uses a new photosensitive material; an aromatic fluorene unit bonded epoxy acrylate resin. The fluorene based resin has interesting properties such as good electrical properties, low curing temperature (160/spl deg/C) for a heat-resistant resin (glass transition temperature, T/sub g/=230/spl deg/C), low coefficient of the thermal expansion (40 ppm), and excellent via hole resolution. Very fine and high-aspect-ratio (>1.0) via holes were formed through exactly the same process steps as those used for a conventional photosensitive epoxy resin; baking, exposure, and development with an aqueous alkaline solution. Another important feature is the technology, that patterns fine-pitch Cu conductors using a semi-additive process with a sputtering method. The DSOL made 40 /spl mu/M very fine pitch Cu conductors on large laminates (330 mm/spl times/400 mm) possible, because this process was composed of flash wet etching of only 0.3 /spl mu/m thick sputtered thin-films. We have successfully developed a high-density packaging substrate for high-pin-count (4000 pins) area array application specific integrated circuit (ASIC) chips.

A novel ultra-thin package for embedded high-pin-count LSI supported by Cu plate

We have developed a thin, low-thermal-resistance LSI package by embedding a high-pin-count LSI chip into ultra-thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 µm, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick Cu plate for cooling, which is much thinner than the conventional flip chip ball grid array (FCBGA) package with a heat sink. Our package shows excellent warpage characteristics, smaller than 82 µm in the temperature range from −55 to +260 °C. Low thermal resistance of 10.8 °C/W is achieved at a wind velocity of 0 m/s, which is also comparable to that of the FCBGA with a large heat sink. We have successfully demonstrated the functions of this package using an LSI tester and personal-computer-like system board. It has also passed a 600-cycle package-level thermal cycle test.

Electrical design and demonstration of an embedded high-pin-count LSI chip package

Design techniques for an ultra-thin LSI package embedding a high-pin-count LSI chip in the thin package substrate have been developed to achieve the excellent electrical performance, as well as low warpage and high heat removal. The embedded chip package we designed is 27 mm by 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against the six metal layers of the product flip chip ball grid array (FCBGA) package using the same chip. Although the two power plane layers have been removed from the substrate, the low impedance of the power distribution network (PDN) is achieved by utilizing many bundles of fine vias. A 0.5-mm-thick copper plate attached to the LSI chips backside provides the signal return path, and contributes to the flatness of this thin package. It also effectively removes heat from the chip. Our design for a product LSI chip with approximately 1,500 pins demonstrates excellent electrical performance as well as small thickness, low warpage, and a high rate of heat removal. Function tests using an LSI tester and a PC-like system board successfully demonstrate the outstanding performance of the LSI chip.

High-performance FCBGA based on multi-layer thin-substrate packaging technology

Abstract We developed a new concept flip-chip ball grid array (FCBGA) based on multi-layer thin-substrate (MLTS) packaging technology in order to meet the strong demand for high-density, high-performance, and low-cost LSI packages. The most important feature of MLTS packaging is that, only a high-density and high-performance MLTS remains by removing the metal plate after mounting an LSI chip. The MLTS packaging offers the advantages of (1) good registration accuracy, which makes higher-density and finer-pitch pattering possible; (2) an ideal multi-layer structure that is highly suitable for high-speed and high-frequency applications; (3) excellent flip-chip mounting reliability, which makes higher-pin-count and finer-pitch area array flip-chip interconnection possible; (4) excellent reliability, supported by use of high T g (glass transition temperature) resin; and (5) a cost-effective design achieved as a result of fewer layers fabricated with fine-pitch patterning. We successfully produced a high-performance FCBGA prototype based on our MLTS packaging technology. The prototype comprises an LSI chip connected to approximately 2500 bonding pads arranged in 240 μm pitch area array, and 1296 I/O pads for BGA. The prototype FCBGA’s excellent long-term reliability was demonstrated through a series of tests conducted on it.

A package-process-oriented multilevel 5-/spl mu/m-thick Cu wiring technology with pulse periodic reverse electroplating and photosensitive resin

A package-process-oriented multilevel 5-/spl mu/m-thick Cu wiring technology has been developed for low resistance power supply wirings in high-speed ULSIs. A thick Cu wiring fabricated by pulse periodic reverse electroplating achieves the good thickness uniformity without CMP process. A photosensitive resin as interlayer dielectric eliminates dry etching steps. Three layers of thick Cu wirings have been successfully fabricated on the top of a 0.13-/spl mu/m CMOS ULSI with three layers of 0.5 /spl mu/m-thick Al wiring. The total thick Cu wiring resistance is confirmed to be five times as small as that of the conventional two layers of 0.5-/spl mu/m-thick Al wirings. This simple technology is suitable for future low-cost ULSI global wirings.

A 5-μm-width multi-layer wafer-level Cu wiring technology with resin CMP for highly-reliable FCBGA

A three-layer wafer-level copper wiring technology adaptable to a large flip-chip ball-grid array (FCBGA) package is successfully developed. This technology features fine 10-mum-pitch copper wiring, with 5-mum thickness, fabricated by a semi-additive process that employs a resin CMP process making each layer flat. A non-photosensitive polyimide is adopted as an insulating material, because it has superior mechanical properties compared to epoxy resin. A prototype chip with a size of 17.3times17.3-mm and three-layer copper wiring is fabricated and packaged into a 50times50-mm FCBGA. This prototype package demonstrates excellent long-term reliability in high-temperature and humidity bias tests (HHBT) and chip-level and package-level thermal-cycle tests (TCTs). Our technology is suitable for future low-cost ULSI wiring and long-distance data-transmission lines in a system-in-package (SiP).

Embedded Active Packaging Technology for High-Pin-Count LSI With Cu Plate

We have developed a thin, reliable, low-thermal-resistance LSI packaging technology by embedding a high-pin-count LSI chip into thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 μm, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick Cu plate for cooling, which is much thinner than the conventional flip chip ball grid array (FCBGA) package with a heat sink. Our package shows excellent warpage characteristics of only 34 μm at room temperature for 27 × 27 mm2 in size. It is also possible to reduce the total package thickness to 0.46 mm by etching the Cu plate to half thickness, with keeping the warpage increase up to 117 μm. Low thermal resistance of 10.8°C/W is achieved for the packages with 0.5-mm-thick Cu plate at a wind velocity of 0 m/s, which is almost comparable to that of an FCBGA with a large heat sink. We have successfully demonstrated the functions of our packages using an LSI tester and personal-computer-like system board. They have also passed a 1000-cycle package-level thermal cycle test.

Reliability of thin seamless package with embedded high-pin-count LSI chip

We have previously reported the technology for embedding a 1500-pin microprocessor chip in a thin LSI package using a rigid Cu plate. The reliabilities of this seamless package with the direct interconnection between the LSI chip and substrate wiring have now been evaluated at the package and board levels. The package passed all the LSI function tests at the package level even after 2000 thermal cycles. The microstructure of the interconnect, evaluated using electron backscatter diffraction and transmission electron microscopy, showed a high interconnect reliability. The reliability at the board level was evaluated using the thermal cycles testing, the shadow-moiré method and strain gauge measurement with the package mounted on a system board. Thanks to the Cu plate, the warpage and strain characteristics are excellent, resulting in uniform stress distribution. Therefore, this seamless packaging technology is promising for the fabrication of thin, highly reliable LSI packages for replacing flip chip ball grid array packages.

Chip-level and package-level seamless interconnect technologies for advanced packaging

Package-process-oriented thick-Cu-wiring technologies have been developed for forming chip-level and package-level seamless interconnects between an LSI chip and the package substrate. Chip-level seamless interconnects are formed using a resin CMP process. Package-level seamless interconnects are formed by embedding a thinned chip into a resin on Cu base plate. A package with package-level seamless interconnects is thinner and has lower thermal resistance, better power delivery, and finer-pitch interconnects than a conventional flip-chip ball grid array package.