Kumiko Nomura

Progress of STT-MRAM technology and the effect on normally-off computing systems

In this paper, the progress of P-MTJs is reviewed and prospects for the normally-off memory hierarchy based on new results are discussed.

Impact of ultra low power and fast write operation of advanced perpendicular MTJ on power reduction for high-performance mobile CPU

We demonstrated lower power consumption of mobile CPU by replacing high-performance (HP)-SRAMs with spin transfer torque (STT)-MRAMs using perpendicular (p)-MTJ. The key points that enable the low power consumption are adapting run time power gating architecture (shown in Fig. 1), and satisfying both fast and low-power writing, namely, 3 nsec and 0.09 pJ, of p-MTJ cell (shown in Fig. 3). As shown in Table 1, only our developed p-MTJ has achieved 3 nsec, 0.09 pJ. Thanks to the fast and low-power p-MTJ, the power consumption of cache memory could be reduced by over 80% without degradation of performance.

Future prospects of MRAM technologies

This paper presents a review and future prospects for the tunnel magnetoresistance (TMR) effect in magnetic tunnel junction (MTJ) and spin manipulation technologies such as spin-transfer torque (STT) for magnetoresistive random access memory (MRAM). Major challenges for ultrahigh-density STT-MRAM with perpendicular magnetization and novel functional devices related to MRAM are discussed.

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture

We have proposed 3 nanoarchitectures with carbon nanotube-based nano-electromechanical systems (CNT-NEMS) switch with a floating gate. It is shown that logic based on them has the potential to replace CMOS using process technology of less than 45 nm. Furthermore, CNT-NEMS-based 3-D circuits realize extremely high bandwidth of over 10 petabyte/s with very low latency of less than several 10 ps. The most effective applications are 3D on-chip crossbar bus and future on-chip network, which will largely determine the performance of future microchips. The performance of 3-D on-chip crossbar based on CNT-NEMS is also compared with that based on CNT-transistors.

Ultra low power processor using perpendicular-STT-MRAM/SRAM based hybrid cache toward next generation normally-off computers

This paper presents novel processor architecture for HP-processor with MRAM/SRAM-based hybrid cache memory. By simulations of HP-processor using MTJs, it has been clarified that total power of the HP-processor using perpendicular-(p-)STT-MRAM [H. Yoda, et al., Current Appl. Phys. 10, e87 (2010)] can be reduced by 50.2% without any degradation of operation speed. This is the first report on effectively decreasing total power of HP-processors with no degradation of performance using magnetic memory. The presented architecture will be the first step to realize the next generation “normally-off computers.”

Variable nonvolatile memory arrays for adaptive computing systems

Magnetic RAM (MRAM) has a unique potential to change its memory capacity from small to large capacity. This paper presents a novel variable circuit based on 1T-1MTJ of perpendicular STT-MRAM memory arrays. It can cover all memory hierarchy and computing units that are variable and adjustable to applications by selecting single, dual or quadruple cell mode and changing circuit resources.

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory

This paper describes a proposal of non-volatile cache architecture utilizing novel DRAM / MRAM cell-level hybrid structured memory (D-MRAM) that enables effective power reduction for high performance mobile SoCs without area overhead. Here, the key point to reduce active power is intermittent refresh process for the DRAM-mode. D-MRAM has advantage to reduce static power consumptions compared to the conventional SRAM, because there are no static leakage paths in the D-MRAM cell and it is not needed to supply voltage to its cells when used as the MRAM-mode. Besides, with advanced perpendicular magnetic tunnel junctions (p-MTJ), which decreases the write energy and latency without shortening its retention time, D-MRAM is capable of power reduction by replacing the traditional SRAM caches. Considering the 65-nm CMOS technology, the access latencies of 1MB memory macro are 2.2 ns / 1.5 ns for read / write in DRAM mode, and 2.2 ns / 4.5 ns in MRAM mode, while those of SRAM are 1.17 ns. The SPEC CPU2006 benchmarks have revealed that the energy per instruction (EPI) of the total cache memory can be dramatically reduced by 71 % on average, and the instruction per cycle (IPC) performance of the D-MRAM cache architecture degraded only by approximately 4 % on average in spite of its latency overhead.

Novel Nonvolatile L1/L2/L3 Cache Memory Hierarchy Using Nonvolatile-SRAM With Voltage-Induced Magnetization Switching and Ultra Low-Write-Energy MTJ

To reduce power consumption of CPU, nonvolatile cache memory has been expected by replacing conventional volatile cache memory based on SRAM. This paper describes nonvolatile cache memory hierarchy design using fast and low-power perpendicular (FL-p-) STT-MRAM. For L3, L2 and L1 cache, 1T-1MTJ with FL-p-STT-MRAM, 6T-2MTJ, and short write pulse based 6T-2MTJ having voltage-induced magnetization switching has been presented for the most suitable combination for the cache memory.

Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies

Three-dimensional integrated circuits (3D-IQ have the potential to reduce interconnect length and improve performance especially in sub-65nm CMOS technologies. This paper describes design and performance analysis of the 3D-IC in sub-65nm CMOS technologies based on the accurate calculation of interconnects delays using 16-core processors as case studies. Performance improvement of the 3D-IC vs. 2D-IC is increased as CMOS scales down, which is consistent with the expected trend. The performance improvement is over 20%. Furthermore, performance of the 3D-IC in 65 nm (or 45 nm) CMOS technology is superior to that of the 2D-IC in 45 nm (or 32 nm) CMOS technology. It indicates that design conversion from 2D-IC to 3D-IC is superior to the CMOS technology migration according to COMS scaling. Reduction in repeater buffers and area overhead is also estimated.

3D on-chip networking technology based on post-silicon devices for future networks-on-chip

We propose a 3D architecture using post-silicon devices, such as nano-mechanical electrical switches, carbon nanotube FETs, and nanowire FETs, for future networks-on-chip (NoC). Based on such a new 3D architecture, extremely high bandwidth with very low latency can be realized. These promising features are very useful for future NoCs