Keiko Morishita

Application of EB repair for high durable MoSi PSM

Recently there has been a demand for high durability MoSi masks. There are some candidates for MoSi mask materials. They are preferable for both mask user and mask manufacture because they show not only high durability against exposure or cleaning process but also process compatibility in production line[1]. They are gaining momentum to practical application. However, there is a drawback for manufacturing regarding the mask repair process. Because ebeam repair employs pure chemical reaction, it faces severe etching difficulty due to higher chemical stability. Meanwhile, the tool supplier has looked into that chemical reaction in detail since the problem was unveiled. They developed a dedicated etching process for high durable materials. It’s so important for the mask manufacturer to evaluate this process properly before they transfer conventional MoSi to new high durability MoSi. A comprehensive understanding of this new process should be acquired by trying several kinds of etching tests. In this paper we will report the results ranging from basic etching rate, selectivity, repair accuracy to flexibility for complicated shaped defects. This data tells us a lot about if it can be applied for practical use. The experiment was performed with e-beam repair tool “MeRiTⓇ”, which was released as the latest version from ZEISS last year. An improved new etching process was applied to “A6L2” type high durable blanks provided by HOYA corporation. A wide variety of programmed defects were arranged on a line and space featured test mask. These programmed defects were repaired with the procedure developed by ZEISS. After repair, printed image was evaluated by AIMSTM system. This paper will discuss the initial results of these first steps into the uncharted territory of high durability MoSi repair.

Defect management of EUV mask

Extreme Ultraviolet Lithography (EUVL) is a promising technology for the fabrication of ULSI devices with 20nm half-pitch node. One of the key challenges before EUVL is to achieve defect-free masks. There are three main categories of mask defects: multilayer defects which cause phase defects, absorber pattern defects, and particles during blank/mask fabrication or mask handling after mask fabrication. It is important to manage multilayer defect because small multilayer defects are difficult to be identified by SEM/AFM after mask patterning and can impact wafer printing. In this paper, we assess blank defect position error detected by 3rd generation blank inspection tool, using blank defect information from blank supplier and 199nm wavelength patterned mask inspection tool NPI-7000. And we rank blank defect in the order of projection defect size to multilayer in order to estimate blank defect printability. This method avoids overestimating the number of potential killer defects that hardly be identified by SEM/AFM under the condition that EUV-AIMS is not available.

Mask defect specification in the spacer patterning process by using a fail-bit-map analysis

We obtained the acceptable mask defect size for both opaque and clear defects in the spacer patterning process using the fail-bit-map analysis and a mask with programmed defects. The spacer patterning process consists of the development of photoresist film, the etching of the core film using the photoresist pattern as the etching mask, the deposition of a spacer film on both sides of the core film pattern, and the removal of the core film. The pattern pitch of the spacer film becomes half that of the photoresist. Both the opaque defect and the clear defect of the mask resulted in a short defect in the spacer pattern. From the fail-bit-map analysis, the acceptable mask defect size for opaque and clear defects was found to be 80nm and 120nm, respectively, which could be relaxed from that in ITRS2008. The difference of the acceptable mask defect size for opaque and clear defects comes from the difference of the defect printability at the resist development.

A noble evaluation method for repaired area utilizing SEM images

In general photomask defect repair process flow, repaired portion is evaluated with AIMSTM and if AIMSTMs result is out of specification, the repaired portion must be re-repaired. With shrinking pattern on device, tighter specification is required. Therefore re-repair cycle time increases and turn around time of defect repair process becomes much longer. To solve this problem, we propose a noble evaluation method that enables us to judge without using AIMSTM with repair tool images. Images of EB repair tool is available for our propose because EB repair tool dose not give any damage on substrate and the resolution of image is quite high compared to other repair tools, FIB and Nanomachining tool. We made lithography simulation and practical experiments with line & space pattern of ArFatt. PSM with programmed defects. Consequently, we can predict AIMS-Results immediately after repair and there is a possibility to reduce the turn around time of defect repair process.

Application of EB Repair Tool for 45nm Generation Photomasks

Although photomask defect repair tools based on FIB, AFM and pulsed laser are mainly used in current production lines, there is a possibility they will not meet the requirements of 45nm generation photomasks. The EB repair tool is one of the candidates that has a possibility of meeting those requirements. The EB repair tool, MeRiT-MGTM, has already been announced by Carl Zeiss GmbH. The basic performance of this tool has been reported.1) Recently MoSi mask is most commonly used in leading edge devices, and defects are mainly opaque type. For this reason, the performance of EB-repair tool for MoSi etching should be investigated. In this paper, we will report the evaluation results of MeRiT-MGTM and consider whether this tool has a possibility of meeting the requirements of 45nm generation photomasks. In order to evaluate the performance of MeRiT-MGTM, we prepared 180nm half pitch line & space pattern of ArFatt. PSM with programmed defects. These programmed defects are not only simple extrusion shape but also of various shapes and sizes. By using these defects, we made practical experiment which would happen in real production line.

Fabrication of Ta based absorber EUV mask with SRAF

With shrinkage of device pattern, optical proximity correction (OPC) will be used for EUV lithography, which leads to need sub resolution assist features (SRAF) on EUV mask. Currently, it is difficult to fabricate EUV mask with SRAF of sub-30nm using conventional resist mask process stably. Moreover, it is necessary to improve line width roughness (LWR) of mask absorber pattern for achieving the lithographic specifications beyond hp15nm patterning. In this paper, in order to meet the requirements of Ta based absorber EUV mask with SRAF, mask fabrication process using new structure blank is studied for sub-30nm SRAF patterning and for improved LWR of primary feature. New mask process using new blank with thinner resist and Cr based hard mask was developed. By using new mask process, resolution of absorber pattern was achieved to 30nm for SRAF patterning, and LWR was improved comparing with conventional process.

DUV inspection beyond optical resolution limit for EUV mask of hp 1X nm

It is generally said that conventional deep ultraviolet inspection tools have difficulty meeting the defect requirement for extreme ultraviolet masks of hp 1X nm. In previous studies, it has been shown that the newly developed optics and systems using deep ultraviolet, named Super Inspection Resolution Improvement method for UnreSolved pattern (SIRIUS), has high sensitivity for nanoimprint lithography templates with unresolved patterns which are the same scale as the wafer. In this paper, the capability of SIRIUS for the extreme ultraviolet mask of hp 1X nm lines and spaces pattern has been studied by evaluating the signal to noise ratio of inspection images and capture rates with 5 runs to the target defects which cause over 10% printed wafer critical dimension errors calculated by simulation. It was demonstrated that the signal to noise ratio was increased and the all target defects became detectable with the throughput of 120 min per 100 × 100 mm2 . Additionally, the printability of natural defects detected with SIRIUS was analyzed. It was confirmed that SIRIUS was able to detect natural defects under 10% of wafer critical dimension. In conclusion, we confirm that SIRIUS can be available for the extreme ultraviolet mask inspection of hp 1X nm lines and spaces pattern.

Application of EB repair for nanoimprint lithography template

Recently, much attention has been paid on nanoimprint lithography (NIL) because of its capability for fabricating device at a low cost without multiple patterning. It is considered as a candidate for next generation lithography technology. NIL is one to one lithography and contact transfer technique using template. Therefore, the lithography performance depends greatly on the quality of the template pattern. And there are some challenges to be solved for defect repair of template because pattern size of template is as same as that of wafer. In order to realize the defect repair of template using electron beam (EB) repair tools, it is necessary to control the EB irradiated area and dose amount of EB repair process more accurately. By optimizing these conditions, EB repair process for template has been improved. In this paper, we evaluated etching repair of a master template and the imprinting to replica. Programmed missing defects on master template were repaired by changing parameters of EB repair tool. It was confirmed that the relationship of critical dimension (CD) and depth of etching repair process for master template and the influence on replica imprinting. As a result, the repair process for master template with hole pattern enables the corresponding CD error of the replica template to be less than ±10% of the target CD.

High-performance fabrication process for 2xnm hole-NIL template production

UV nano imprint lithography (UV-NIL) has high-throughput and cost-effective for complex nano-scale patterns and is considered as a candidate for next generation lithography tool. In addition, NIL is the unmagnified lithography and contact transfer technique using template. Therefore, the lithography performance depends greatly on the quality of the template pattern. According to ITRS 2013, the minimum half pitch size of Line and Space (LS) pattern will reach 1x nm level within next five years. On the other hand, in hole pattern, half pith of 2x nm level will be required in five years. Pattern shrink rate of hole pattern size is slower than LS pattern, but shot counts increase explosively compared to LS pattern due to its data volume. Therefore, high throughput and high resolution EB lithography process is required. In previous study, we reported the result of hole patterning on master template which has high resolution resist material and etching process. This study indicated the potential for fabricating 2xnm hole master template [1]. After above study, we aim at fabricating the good quality of 2xnm master template which is assured about defect, CD uniformity(CDU), and Image placement(IP). To product high quality master template, we develop not only high resolution patterning process but also high accuracy quality assurance technology. We report the development progress about hole master template production.

The quality assurance of EUV mask pattern based on 3D-SEM and lithography simulation

Extreme Ultra Violet (EUV) lithography is a leading candidate technology to succeed ArF lithography for high-volume manufacturing (HVM) in the next generation. A serious obstacle to the realization of EUV lithography is that the evaluation tool for EUV masks is insufficient. In particular, although the evaluation of mask pattern quality by means of an aerial image is essential for the supply of defect-free masks, timely establishment of EUV AIMS operation is difficult. We are developing a system that evaluates the printability to wafer of a mask pattern by a combination of mask pattern measurement using three-dimensional (3D) SEM and wafer image prediction using lithography simulation. The measurement of the mask pattern is a key technique of the system. It is performed by 3D-SEM, which enables the highly accurate measurement of the mask pattern sidewall angle using a tilted SEM image. Because EUV lithography is off-axis illumination on a mask pattern, the sidewall angle management of a mask pattern is important. Besides, 3D-SEM acquires a mask pattern image with high resolution and wide area. The wafer image can be predicted with high accuracy on the basis of the 3D mask pattern data, which are highly accurate and cover a wide area. In this paper, we describe the method of 3D mask pattern data measurement. Additionally, we report the experimental results concerning the 3D mask pattern measurements and the wafer image predictions.