Barry P. Linder

Dielectric breakdown mechanisms in gate oxides

In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...

The impact of gate-oxide breakdown on SRAM stability

We have investigated the effects of oxide soft breakdown (SBD) on the stability of CMOS 6T SRAM cells. Gate-to-diffusion leakage currents of 20-50 /spl mu/A at the n-FET source can result in a 50% reduction of noise margin. Breakdown at other locations in the cell may be less deleterious depending on n-FET width. This approach gives targets for tolerable values of leakage caused by gate-oxide breakdown.

Voltage dependence of hard breakdown growth and the reliability implication in thin dielectrics

Hard breakdown (HBD) is shown to be a gradual process with the gate current increasing at a predictable rate exponentially dependent on the instantaneous stress voltage and oxide thickness. This is contrary to conventional wisdom that maintains that HBD is a fast thermally driven process. The HBD degradation rate (DR) for a 15 /spl Aring/ oxide scales from >1 mA/s at 4 V to <1 nA/s at 2 V, extrapolating to <10 fA/s at use voltage. Adding the HBD evolution time to the standard time-to-breakdown potentially reduces the projected fail rate of gate dielectrics by orders of magnitude.

A model for gate-oxide breakdown in CMOS inverters

The effect of oxide breakdown (BD) on the performance of CMOS inverters has been investigated. The results show that the inverter performance can be affected by the BD in a different way depending on the stress polarity applied to the inverter input. In all the cases, the oxide BD conduction has been modeled as gate-to-diffusion leakage with a power-law formula of the type I=KV/sup p/, which was previously found to describe the BD in capacitor structures. This implies that the BD physics at oxide level is the same as that at circuit level.

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

We have fabricated electrically reliable band-edge (BE) high-k/metal nMOSFETs stable to 1000degC, that exhibit the highest mobility (203 cm2/Vs @ 1MV/cm) at the thinnest Tinv (1.4 nm) reported to date. These stacks are formed by capping HfO2 with ultra-thin layers containing strongly electropositive gp. IIA and IIIB elements (e.g. Mg and La), prior to deposition of the TiN/Poly-Si electrode stack, in a conventional gate-first flow. Increasing the cap thickness tunes the Vt/V fb from a midgap position to BE while maintaining high mobility and good PBTI. The addition of La can enhance the effective k value of the dielectric stack, resulting in EOTs < 1nm. Short channel devices with band edge characteristics are demonstrated down to 60 nm. Finally, possible mechanisms to explain the nFET Vt shift are discussed

Examination of flatband and threshold voltage tuning of HfO2∕TiN field effect transistors by dielectric cap layers

The authors have examined the role of sub nanometer La2O3 and LaN cap layers interposed in Si∕HfO2∕TiN high-k gate dielectric stacks in tuning the flatband and threshold voltages of capacitors and transistors. High performance, band edge n metal oxide field effect transistors with channel lengths down to 60nm may be fabricated without significant compromise in mobility, electrical thickness, and threshold voltage. They have carried out a microstructural evaluation of these stacks and correlated these results with the electrical behavior of the devices.

Gate oxide breakdown under Current Limited Constant Voltage Stress

Ultra-thin oxide reliability has become an important issue in integrated circuit scaling. Present reliability methodology stresses oxides with a low impedance voltage source. This, though, does not represent the stress under circuit configurations, in which transistors are driven by other transistors. A Current Limited Constant Voltage Stress simulates circuit stress well. Limiting the current during the breakdown event reduces the post-breakdown conduction. Limiting the current to a sufficiently low value may prevent device failure, altogether.

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å Tinv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFETs fabricated with gate-first high thermal budget processing with thin Tinv (≪13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFETs into CMOS devices yielded large SRAM arrays.

Growth and scaling of oxide conduction after breakdown

Hard breakdown is shown to be a gradual process with the gate current increasing at a predictable rate, exponentially dependent on the instantaneous stress voltage. Adding the hard breakdown evolution time to the standard time to breakdown potentially reduces the projected fail rate of gate dielectrics by orders of magnitude. The scaling of the hard breakdown growth rate with respect to device area, substrate doping, oxide thickness, and channel length are explored. A two-voltage stress procedure is introduced that measures degradation rates on sub-micron devices several orders of magnitude more quickly than a conventional single voltage stress.

Fundamental aspects of HfO 2 -based high-k metal gate stack reliability and implications on t inv -scaling

Experimental reliability trends indicate that tinv-scaling with HKMG stacks remains challenging because NBTI, PBTI and TDDB reliability margins rapidly decrease with decreasing tinv values and increasing gate leakage current. A case is made that these observed trends arise from the layer structure and the materials properties of the SiO(N)/HfO2 dual dielectric. Therefore, fundamental reliability limitations appear to increasingly impact HKMG stack scaling.