Shyue-Shyh Lin

A 25-nm gate-length FinFET transistor module for 32nm node

FinFET is the most promising double-gate transistor architecture [1] to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-FinFET have 1200 and 915 µA/µm drive current respectively at 100nA/µm leakage under 1V. To our knowledge this is the best FinFET drive current at such scaled gate length. This scaled gate length enables this FinFET transistor for 32nm node insertion. With aggressive fin pitch scaling, the effective transistor width is approximately 1.9X and 2.7X over planar for typical logic and SRAM on the same layout area (i.e., silicon real estate). Due to superior electrostatics and reduced random dopant fluctuation, this high drive current can be readily traded with VDD scaling for low power.

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

We show that FinFET, a leading transistor architecture candidate of choice for high performance CPU applications [1–3], can also be extended for general purpose SoC applications by proper device optimization. We demonstrate superior, best-in-its-class performance to our knowledge, as well as multi-Vt flexibility for low-operating power (LOP) applications. By high-k/metal-gate (HK/MG) and process flow optimizations, significant drive current (ION) improvement and leakage current (IOFF) reduction have been achieved through equivalent oxide thickness (EOT) scaling and carrier mobility improvement. N-FinFET and P-FinFET achieve, when normalized to Weff (Weff=2xHf+Wf), ION of 1325 µA/µm and 1000 µA/µm at 1 nA/µm leakage current under VDD of 1 V, and 960 uA/um and 690 uA/um at 1 nA/um under Vdd of 0.8V, respectively. This FinFET transistor module is promising for a 32/28nm SoC technology.

4K-cells Resistive and Charge-Base-Capacitive Measurement Test Structure Array (R-CBCM-TSA) for CMOS Logic Process Development, Monitor and Model

To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for CMOS logic process development, monitor and model. The test chip utilizes 4-terminal (one of 4 is strongly grounded) Kelvin force/sense measurement for resistive-type and charge-base capacitance measurement (CBCM) for capacitive-type test structures. With the aid of memory-addressing design scheme, any one of the device-under-test in an array can be randomly or sequentially selected for testing with all of them sharing a common probe pad group. To accelerate the testing speed, the address control signals of 8 test structure array are connected in parallel for synchronized parallel testing. A 32×16×8 test structure array has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The results confirm the excellence of this architecture in measurement with 0.1fF for capacitive and 0.1 ohm for resistive systematic errors, and 7 times testing speed improvement.

Library-based process test vehicle design framework

This work describes a test vehicle design framework, which minimizes the discrepancy among design rule set, tests structure design and testing plan. The framework is composed of the symbolic design rule set, Parametereized-Device, test structure generator, and test vehicle generator. An approach for simplification and consolidation of test structure is proposed to derive the concise test structure library. Finally, implementation of test vehicle is presented.

Design and integration of electrical-based dimensional process-window checking infrastructure

The purpose of this work is to provide a design infrastructure for electrical-based dimensional process-window checking. With the aid of the novel test vehicle design platform, the discrepancy among design rule set, test structure design and testing plan can be minimized. Using the function-independent Test Structure Design Intellectual Properties (TSD-IP) provided by this infrastructure, the process-window could be quantified as the electrical testing of test structures. A cross-generation (130 nm-90 nm) test vehicle which focuses on the evaluation of overlay and critical dimension variation across the intra- and inter-photo field is enacted to demonstrate the design framework.

Defect detection for short-loop process and SRAM-cell optimization by using addressable failure site-test structures (AFS-TS)

This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

Using genetic algorithm to optimize the dummy filling problem of the flash lamp anneal process in semiconductor manufacturing

In deep sub-micron era, many semiconductor fabrication process variations highly relate to uniformity of IC layout design. Chemical-polishing process and Flash Lamp Anneal (FLA) are two of the crucial processes aiming to increase uniformity of IC. Dummy filling is an efficient and effective Design for Manufacturability method for increasing layout uniformity by filling non-functional dummy shapes onto unoccupied area and thus reducing pattern-induced process variation. However, none are design for the thermal effects of FLA process. FLA process annealed the wafer in high temperature (1250°C) in a few milliseconds. Wafer surface emissivity determines the amount of heat absorption during FLA process. The temperature variation of FLA process induced by surface emissivity variation of IC layout results in shifts of transistors’ electrical parameters. This paper proposed to use genetic algorithm to minimize the emissivity variation of IC layout by filling a series of prescribed dummy patterns with various emissivity. The experimental results from twenty test cases show that 35% emissivity variation reductions can be achieved and moreover the observed temperature deviation during FLA is under 2.8%.

A Clustering Analysis Model for Golden Die Extractions Based on Wafer Acceptance Test at Semiconductor R&D Stage

During the research and development (R&D) stage of semiconductor fabrication, the R&D engineers make a lot of effort to identify golden dice that meet simulated performance of circuit design. With feedback from wafer acceptance test (WAT) data of the golden dice, the efficiency of process window analysis can be further improved. However, it is difficult for current practices to select golden dice due to limited time and cost concerns. In this research, an analytical model is proposed to analyze WAT data during the R&D stage of semiconductor fabrication to assist R&D engineers in resolving these critical issues. WAT data are collected and utilized to classify dice on a wafer and similar golden dice are then identified based on pre-defined golden dice. Similar golden dice can provide much more important feedback from WAT data, and the efficiency of process window analysis can then be improved. Real WAT data at the R&D stage during semiconductor fabrication were collected from a famous semiconductor manufacturing company and were experimented through the presented methodology. Experimental results show that the presented model can successfully extract representative similar golden dice within clusters. With advice from R&D engineers, the representative similar golden dice extracted from this work are sufficient for subsequent process window analysis.

Global pattern density effects on low-k trench CDs for sub-65-nm technology nodes

Comprehensive CD characterization of low-k trench etch for 65nm nodes are performed through a specially designed mask with global pattern density (GPD) in the range from 25% to 60%. Unlike traditional means, through this mask we systematically demonstrate global pattern density effects on etch behaviors in correlation with CD uniformity, CD proximity, and CD linearity without local etch loading effect contributed from nearby environment [1-3] and position dependent effect contributed from resist developing or aberrations of the wafer-imaging lens [4]. From our study, CD proximity is the most sensitive item. Wider trench shows larger CD variation as compared with narrow trench when global environment vary. Moreover, we find that low pressure etch conditions in a small chamber volume etcher exhibits less CD variation of global pattern density effect. On the other hand, pressure in a large chamber volume etcher provides better tuning capability in the adjustment of CD variation. The results suggest that residence time might be an influential factor for the GPD dependent CD control.

A test structure to verify the robustness of silicided N+/P+ interface

We propose a new test structure that provides a single current path for silicide robustness detection at N+/P+ butted well tap interface with good sensitivity. Two reference test structures suspected with more than one current path and consequently give false results are also compared for structure and electrical performances.