Tetsuaki Nakamikawa

Design and evaluation of the high performance multi-processor server

The paper discusses the architecture and performance of a prototype RISC multi-processor server designed for a business system like OLTP (online transaction processing). The combination of a low-latency cache-to-cache copy and an 8-way highly interleaved main memory realize high performance for the OLTP program. We analyzed the activity of the multi-processor system when executing the OLTP program by using the trace-driven simulator including kernel execution. The main findings are that: cache misses due to task migration and ping-ponging of kernel shared data occupy a larger part of the total misses, especially in a large cache capacity because of intensive I/O activities; and the low-latency cache-to-cache copy is very effective because 50-60% of the data read accesses are supplied by the cache-to-cache copy in a large cache capacity.<<ETX>>

High performance fault tolerant computer and its fault recovery

The authors proposed a new architecture for an FTC called QPR (Quad Processor Redundancy) in which duplicated CPUs operate under a hardware lock step, and duplicated I/Os are managed by software. A dual system bus combines two duplicated areas. After recovery from a fault, it is necessary to resynchronize the system, so the contents of the main memory must be copied from the normal CPU to the other CPU. The overhead for copying must be small, so that the normal CPU can still continue the application. They describe a fault recovery method especially for a memory copying method. When a memory access has occurred, the memory interface unit snoops the data and sends them to another CPU using the dual system bus. They measured copy time using the real machine and simulated the copy overhead under a heavy DMA load. They obtained a small overhead and small load dependency.

A floating point processing unit for the Gmicro CPU

This paper describes the architecture and implementation of a newly developed floating point processing unit (FPU). It was developed as a high performance 32-bit coprocessor of the 32-bit Gmicro microprocessor, which satisfies the IEEE 754 Standard for Binary Floating-Point Arithmetic.