Takao Kumihashi

Process and properties of Pt/Pb(Zr, Ti)O3/Pt integrated ferroelectric capacitors

Abstract A one-mask-patterned ferroelectric capacitor memory cell structures designed with a 0.5-μm feature size were fabricated. Oxygen plasma treatment after dry etching decreased the leakage current to as low as as-deposited film. The one-mask-patterned ferroelectric capacitors with switching charge almost equal to as-deposited film were achieved. Ferroelectric memories as dense as dynamic random access memories will become possible with this technology.

Short‐gas‐residence‐time electron cyclotron resonance plasma etching

This paper describes short‐gas‐residence‐time electron cyclotron resonance plasma etching for high etch rates, reduced contamination, and highly anisotropic etching. The new high‐gas‐flow‐rate (high‐flow) etching system is demonstrated with effective‐pumping rate of 2500 l/s. This method produces very high etch rate while maintaining high anisotropy at very low gas pressure below 1 mTorr. The high etch rate is due to the reduction of reaction products density because of the very short gas‐residence time of 30 ms. This technique also dramatically reduces the contamination of reaction products. Etching of crystalline Si and n+ polycrystalline Si with the high‐flow etching system is demonstrated. For crystalline Si etching with Cl2, a high etch rate up to 1 μm/min is achieved at a high gas flow rate of 90 sccm at 0.5 mTorr.

A 7.03-/spl mu/m/sup 2/ Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching

A ferroelectric memory cell with an area of only 7.03 /spl mu/m/sup 2/ designed with a 0.5-/spl mu/m rule has been fabricated. It performs Vcc/2-plate nonvolatile DRAM operation: ordinary DRAM operation and automatic nonvolatile writing when Vcc is shut down. A non-separated plate electrode and a capacitor patterned by one-mask dry etching reduce cell area. Planarization of the poly-Si plugs and the use of H-less metallization/passivation processes retain the PZT capacitor characteristics (Pr=50 fC/bit) and achieves ferroelectric write/read under /spl plusmn/2.5-V operation in 4-K bit memory cell arrays.

Novel short‐gas‐residence‐time electron cyclotron resonance plasma etching

Novel short‐gas‐residence‐time electron cyclotron resonance (ECR) plasma etching is described. Using a newly equipped high‐pumping‐rate etching system (5000 l/s), we obtained a high etch rate and high anisotropic etching of silicon at low pressure and high gas flow rate. The residence time obtained was 30 ms. The silicon etch rate with Cl2 dramatically increased up to 1 μm/min as the gas flow rate increased to 90 sccm at 0.5 mTorr. It was proven by plasma emission measurement that the reaction products were minimized by the present method. These results indicate that the short‐gas residence time produces a small amount of reaction products and a large amount of etching species.

Sub-Quarter-Micron Pt Etching Technology Using Electron Beam Resist with Round-Head

Pt patterns of 0.16, 0.25 and 0.36 µm size and without a sidewall-fence were formed using dipole ring magnetron reactive ion etcher (DRM-RIE) with round-head resist masks of 0.1, 0.2 and 0.28 µm size written by an electron beam. Critical dimension (CD) gains ranged from 50 to 60 nm, and taper angles ranged from 72 to 75°. To realize sidewall-fence-free Pt etching with a small CD gain and large taper angle, it is important to tune resist selectivity to an optimum. Taper angle becomes small and CD gain becomes large in the case of low resist selectivity; on the other hand, sidewall-fence is formed in the case of high resist selectivity. Eventually, under the condition of optimum resist selectivity, no sidewall-fence is formed and taper angle and CD gain become large and small, respectively. The optimum resist selectivity has been realized under the conditions of low pressure, high Cl2 flow rate, and high RF power.

A scalable single-transistor/single-capacitor memory cell structure characterized by an angled-capacitor layout for megabit FeRAMs

A single-transistor/single-capacitor ferroelectric random access memory (FeRAM) cell having a cell size of 4.5 /spl mu/m/sup 2/ has been developed using 0.5-/spl mu/m technology. This cell features a stacked capacitor structure with a poly-Si plug and an angled-capacitor layout. This unique capacitor layout increases the alignment tolerance between the plate contact and the individual capacitor electrodes without increasing the cell area. O/sub 2/ annealing was applied after the plate-contact formation to restore the remanent polarization degradation. Favorable ferroelectric capacitor characteristics were observed when this cell was used in an experimental 4-Kbit memory-cell array.

Reduction in Microloading by High-Gas-Flow-Rate Electron Cyclotron Resonance Plasma Etching

High-gas-flow-rate electron cyclotron resonance plasma etching was employed to reduce microloading in Si etching with Cl2 at low pressure. Microloading estimated with a conventional etching system increases with decrease in pressure from 5 to 0.5 mTorr. The increase in microloading is attributed to the increase in the ratio of ion flux to reacting neutrals. The ion/neutral ratio was found to be as large as 6.4 at 0.5 mTorr. This large ratio was caused by both the decrease in reacting neutral density and the increase in reaction products. The high gas flow rate with a high effective pumping speed of 2000 l/s reduces the reaction products, increases the reacting neutrals and reduces the ion/neutral ratio to 0.65. As the result, the microloading is reduced. The relative etch rate at an aspect ratio of 7 increases from 0.65 at 136 l/s to 1.00 at 2000 l/s. Thus high-gas-flow-rate-etching solved the problem of large microloading which is not suppressed even with high density plasma and low gas pressure.

High-rate-gas-flow microwave plasma etching of silicon

A high-rate-gas-flow plasma etching technique using a very low gas pressure and very high pumping rate is described. The principle of high-flow etching is discussed. A high etch rate of 1300 nm/min at 0.5 mtorr has been obtained for the Cl/sub 2/ ECR high-flow system with a bias of -50 V. Low gas pressure discharge with high flow rate is applicable to VLSI processing. Highly directional, low-contamination etching is possible using this etching system.<<ETX>>

An etching model to predict minimum-microloading gas pressure

Plasma etching has been widely used in fabricating ultra large-scale integrated circuits (ULSI). One etching problem, however is that the etching rate decreases with decreasing pattern width; this is called microloading. Up to now, ion shadowing microloading was suppressed by using lower gas pressure. However, as the pressure decreases, another type of microloading is caused by reactant limiting or product adsorption. Recently, we found that the etching rate was related to reactant and product surface diffusion in the adsorption process. Our model incorporating this process has shown these types of microloading decrease as the pressure increases, in contrast to ion shadowing microloading. Therefore, there must be an optimum gas pressure that minimizes microloading. We can determine this pressure using our etching model which involves an ion shadowing term. This model is applied here to Cl/sub 2/-gas Si etching and Al etching.

Characteristic Secondary Electron Emission from Graphite and Glassy Carbon Surfaces

Secondary electron emissions (SEE) from graphite and glassy carbon surfaces have been measured. The spectra give several characteristic peaks whose energies are independent of incident electron energies from 20 to 2500 eV. It has been proved that the SEE spectra show good agreement with core electron excitation energy loss spectra and with the calculated density of state (DOS) of the conduction band. Thus, the SEE spectra directly reflect the conduction band DOS above vacuum level, and the difference between the spectra of graphite and glassy carbon comes from the difference in their conduction band structures.