Kazuhiko Hashimoto

Choice of power-supply voltage for half-micrometer and lower submicrometer CMOS devices

The tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFETs. Some guidelines for optimum power-supply voltage and process/device parameters for half-micrometer and lower submicrometer CMOS devices are proposed in order to maintain MOS device reliability and achieve high circuit performance. It is shown that power-supply voltage must be reduced to maintain reliability and improved performance and that the optimum voltage reduction follows the square root of the design rule. Trends for scaling down power-supply voltage have been experimentally verified by results obtained from measurements on CMOS devices over a wide range of gate oxide thickness (7-45 nm) and gate lengths (0.3-2.0 mu m). >

Behavior of ion‐implanted As atoms in Si during molybdenum disilicide formation

The behavior of ion implanted As atoms during MoSi2 formation has been investigated by I‐V measurement and neutron activation analysis. I‐V characteristics of the MoSi2/Si interface was rectifying indicating that the impurity concentration in Si is very low. Arsenic atoms implanted in the Si substrate were found to redistribute toward the MoSi2/Si interface, but not into the underlying Si. The reason for no enhanced diffusion of As during MoSi2 formation has been discussed in terms of point defects which are not likely to be generated for the silicides in which Si is the dominant diffusing species.

Evaluation of Spatial Distribution of Hole Traps Using Depleted Gate MOSFETs

The distribution of hole traps in the gate oxide of metal-oxide-semiconductor field effect transistors (MOSFETs) is evaluated with capacitance-voltage measurements using depleted polysilicon gate MOSFETs. Nonavalanche hole injection from the substrate shows that the average distance of hole traps from the SiO2/Si-substrate interface is 3.7 nm for MOSFETs with a 10-nm gate oxide. The experiment of a Fowler-Nordheim electron injection after the hole injection indicates that electron traps created during the hole injection exist at a distance in the range of 2.5-6 nm from the SiO2/Si-substrate interface, suggesting that hole traps also exist in the same region.

N-Channel MNOS EAROM for TV Electronic Tuning System

A new n-channel MNOS technology for EAROM applications has been developed by introducing a threshold voltage control technique. The technology is principally based on a low energy implantation of boron ions for obtaining a positive center voltage in the threshold window, which results in better retentivity. By incorporating this MNOS technology and n-well CMOS technology on an isolated epitaxial layer, an n-channel MNOS EAROM is fabricated for TV electronic tuning system. The EAROM utilizes the two MNOS transistors per cell configuration. The device showed a long data retention time over 10 years at 80 °C after 105 erasing/writing cycles, therefore the technology appears to be quite promising for EAROM applications.