Kenneth Francken

A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators

An approach is presented for the high-level simulation and synthesis of discrete-time /spl Delta//spl Sigma/ modulators based on a simulation-based optimization strategy. The high-level synthesis approach determines both the optimum modulator topology and the required building block specifications, such that the system specifications-mainly accuracy (dynamic range) and signal bandwidth-are satisfied at the lowest possible power consumption. A genetic-based differential evolution algorithm is used in combination with a fast dedicated behavioral simulator to realistically analyze and optimize the modulator performance. The approach has been implemented in a tool called Daisy (Delta-Sigma Analysis and Synthesis). Experimental results are shown for both the analysis and synthesis capabilities, illustrating the effectiveness of the approach. The selected range of optimized /spl Delta//spl Sigma/ modulator topologies as a function of the modulator specifications for a wide range of values indicate the capabilities of and the performance range covered by the tool.

DAISY: a simulation-based high-level synthesis tool for /spl Delta//spl Sigma/ modulators

An integrated tool called DAISY (Delta-Sigma Analysis and Synthesis) is presented for the high-level synthesis of /spl Delta//spl Sigma/ modulators. The approach determines both the optimum modulator topology and the required building block specifications, such that the system specifications mainly accuracy and signal bandwidth-are satisfied at the lowest possible power consumption. A genetic-based differential evolution algorithm is used in combination with a fast dedicated behavioral simulator that includes the major nonidealities of the building blocks to realistically analyze and optimize the modulator performance. Experimental results illustrate the effectiveness of the approach. Also, an overview of optimized topologies as a function of the modulator specifications for a wide range of values shows the capabilities and performance range covered by the tool.

An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators

Circuit-level simulation of /spl Delta//spl Sigma/ modulators is a time-consuming task, taking one or more days for meaningful results. While there are a great variety of techniques and tools that speed up the simulations for discrete-time /spl Delta//spl Sigma/ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time counterpart. Nevertheless, in todays low-power, high-accuracy and/or very high-speed demands for A-to-D converters, designers are often forced to resort to the use of continuous-time /spl Delta//spl Sigma/ topologies. In this paper, we present a method for the high-level simulation of continuous-time /spl Delta//spl Sigma/ modulators as needed in top-down design and high-level modulator optimization. The method is based on analytical integration using behavioral models and exhibits the best tradeoff between accuracy, speed, and extensibility in comparison with other possible techniques that are reviewed briefly in this work. This methodology has been implemented in a user-friendly tool. Nonidealities such as finite gain, finite GBW, output impedance, and also nonlinearities, such as clipping, harmonic distortion, and the important effect of jitter are modeled. Finally, the tool was used to carry out some design-relevant experiments, illustrating the straightforward way of obtaining and exploring design tradeoffs at the modulator architectural level.

An efficient, fully parasitic-aware power amplifier design optimization tool

A methodology for the optimal parasitic-aware design of RF power amplifiers toward maximum power efficiency is presented. It is based on a template-driven simulation-based optimization approach, including the effect of all device parasitics (transistors, passives) during the sizing. The combination of expert knowledge (in the template) with a state-of-the-art evolutionary algorithm results in a highly flexible and optimal sizing methodology tailored to RF circuits. Parasitic information is obtained through interaction with device profilers. The methodology is implemented in a fully featured software tool called M-DESIGN and is applied to the optimal sizing of a two-stage Class E power amplifier for maximum efficiency. The complete sizing was obtained in less than one hour of CPU time. Moreover, the constraint templates that were used are presented and discussed. An amplifier manufactured in a commercial 0.35-/spl mu/m 5M2P CMOS process and sized using the proposed methodology shows a maximum value of 67% for the drain efficiency (DE) versus 66% simulated. Measurement results show that it works at 850 MHz and has a maximum output power of 30 dBm at 2.3 V. The power-added efficiency (PAE) is always greater than 60% for an output power above 160 mW and a maximum PAE of 66% is achieved.

Methodology for analog technology porting including performance tuning

A methodology for technology porting of analog circuit designs is presented. Both the sizing and the layout phase are discussed. The sizing methodology can also be used to tune performances (e.g. minimizing power consumption) when there are margins on the specifications. The methodology is successfully applied to a high-speed /spl Delta//spl Sigma/ A/D converter that is ported from a 0.5 /spl mu/m to a 0.35 /spl mu/m CMOS process.

A behavioral simulation tool for continuous-time ΔΣ modulators

Circuit--level simulation of ΔΣ modulators is a time--consuming task (taking one or more days for meaningful results). While there are a great variety of techniques and tools that speed up the simulations for discrete--time (DT) ΔΣ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous--time (CT) counterpart. Yet, in todays low--power, high--accuracy and/or very high--speed demands for A--to--D converters, designers are often forced to resort to the use of CT ΔΣ topologies. In this paper, we present a method for the high--level simulation of continuous--time ΔΣ modulators that is based on behavioral models and which exhibits the best trade--off between accuracy, speed and extensibility compared to other possible techniques that are reviewed briefly in this work. A user--friendly tool, implementing this methodology, is then presented. Nonidealities such as finite gain, finite GBW, output impedance and also nonlinearities such as clipping, harmonic distortion and the important effect of jitter are modeled. Finally, experiments were carried out using the tool, exploring important design trade--offs.

A behavioral simulation tool for continuous-time /spl Delta//spl Sigma/ modulators

Circuit-level simulation of /spl Delta//spl Sigma/ modulators is a time-consuming task (taking one or more days for meaningful results). While there are a great variety of techniques and tools that speed up the simulations for discrete-time (DT) /spl Delta//spl Sigma/ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time (CT) counterpart. Yet, in todays low-power, high-accuracy and/or very high-speed demands for A-to-D converters, designers are often forced to resort to the use of CT /spl Delta//spl Sigma/ topologies. In this paper, we present a method for the high-level simulation of continuous-time /spl Delta//spl Sigma/ modulators that is based on behavioral models and which exhibits the best trade-off between accuracy, speed and extensibility compared to other possible techniques that are reviewed briefly in this work. A user-friendly tool, implementing this methodology, is then presented. Nonidealities such as finite gain, finite GBW, output impedance and also nonlinearities such as clipping, harmonic distortion and the important effect of jitter are modeled. Finally, experiments were carried out using the tool, exploring important design trade-offs.

Dedicated system-level simulation of /spl Delta//spl Sigma/ modulators

A new approach is presented for significantly speeding up system-level simulation of /spl Delta//spl Sigma/ modulators. The method is based on high-level simulation that can be combined with an acceleration algorithm and has been implemented in C. Also, the decimator has been included yielding a complete and fast simulation of the whole converter. This reduces the bottleneck seen in system-level simulation of complete systems, e.g. receiver front-ends. Different topologies are included as well as the effects of most important nonidealities. Experimental results show the effectiveness of the approach.

Knowledge- and optimization-based design of RF power amplifiers

Some of the problems that threaten analog design are the reduction of power supply voltage and the decreasing MOS threshold voltages that are inherent to modern process technologies. At the same time it becomes increasingly difficult to take parasitic effects into account. Yet, it is a common trend to integrate even analog RF circuits in todays systems-on-chip. In this paper we targeted the optimization of an RF power amplifier. To this end, we first derived the state-space model equations. After summarizing the limitations of this approach we then present a sizing tool specifically tailored toward the design of optimal RF circuits. This tool is then used for optimally sizing two class E power amplifiers. The result of one experiment compare favorably to a published and measured design.

PROCESS MIGRATION TOOLS FOR ANALOG AND DIGITAL CIRCUITS

The rapid progress in CMOS VLSI technologies together with the shortening time-to-market constraints of a competitive market and the shortage of designers necessitates the use of computer-aided design (CAD) tools for the automatic porting of existing designs from one technology process to another. Both horizontal and vertical technology porting are considered, where during vertical porting the intrinsically better capabilities of the new process can be exploited to either improve the performance of the circuit, or to keep the same performance while reducing power and/or chip area consumption.