P. Vancorenland

A 900-mV low-power /spl Delta//spl Sigma/ A/D converter with 77-dB dynamic range

The design of a low-voltage and low-power /spl Delta//spl Sigma/ analog-to-digital (A/D) converter is presented. A third-order single-loop /spl Delta//spl Sigma/ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV /spl Delta//spl Sigma/ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-/spl mu/W power consumption.

A layout-aware synthesis methodology for RF circuits

In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling and integrated layout generation to synthesize RF Circuits efficiently, taking into account all layout parasitics during the circuit optimization. The proposed approach has successfully been applied to the design of a high-performance downconverter mixer circuit, proving the effectiveness of the implemented design methodology.

A 1.57-GHz fully integrated very low-phase-noise quadrature VCO

A very low-phase-noise quadrature voltage-controlled oscillator is presented, featuring an inherently better figure of merit than existing architectures. Through an improved circuit schematic and a special layout technique, the phase noise of the circuit can be lowered. The circuit draws 15 mA from a 2-V supply. The phase noise is -133.5 dBc/Hz at 600 kHz and the tuning range is 24% wide at a center frequency of 1.57 GHz.

DAISY: a simulation-based high-level synthesis tool for /spl Delta//spl Sigma/ modulators

An integrated tool called DAISY (Delta-Sigma Analysis and Synthesis) is presented for the high-level synthesis of /spl Delta//spl Sigma/ modulators. The approach determines both the optimum modulator topology and the required building block specifications, such that the system specifications mainly accuracy and signal bandwidth-are satisfied at the lowest possible power consumption. A genetic-based differential evolution algorithm is used in combination with a fast dedicated behavioral simulator that includes the major nonidealities of the building blocks to realistically analyze and optimize the modulator performance. Experimental results illustrate the effectiveness of the approach. Also, an overview of optimized topologies as a function of the modulator specifications for a wide range of values shows the capabilities and performance range covered by the tool.

A fully-integrated GPS receiver front-end with 40 mW power consumption

A 0.25 /spl mu/m CMOS quadrature complex bandpass low-IF GPS receiver includes an LNA, PLL, mixer and a continuous-time /spl Delta//spl Sigma/ ADC. The chip has -130 dBm input sensitivity, 62 dB DR, and -32 dB IMRR, while consuming 40 mW from 2 V supply. The chip is 9 mm/sup 2/.

CMOS: a paradigm for low power wireless?

An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low costs, both in the CMOS technology as well as the power.

CYCLONE: automated design and layout of RF LC-oscillators

This paper presents an automated, layout-aware RF LC-oscillator design tool, called CYCLONE that delivers an accurate and optimal LC-oscillator design, from specification to layout. The tool combines the accuracy of device-level simulation and finite element analysis with the optimisation power of simulated annealing algorithms and is verified with experimental results.

A 900 mV 40 /spl mu/W switched opamp /spl Delta//spl Sigma/ modulator with 77 dB dynamic range

Portable electronic systems require low-voltage low-power building blocks. An important building block is an A/D converter. /spl Delta//spl Sigma/ ADCs provide an efficient way of trading off speed for resolution. The switched op amp (SO) technique allows design of switched-capacitor (SC) circuits at very low supply voltage without the use of multithreshold technologies or voltage multipliers to drive the switches. The basic idea of it is to leave out the switches connected to the output of the amplifier in a SC integrator, because those are the ones that fail to conduct when the supply voltage is low. Switches can only be connected to well-chosen reference voltages. In this implementation the differential modified SO integrator cell is used, so the reference voltages are V/sub SS/ and V/sub DD/. This allows maximum overdrive of V/sub DD/-V/sub SS/ for the switches.

A quadrature direct digital downconverter

A quadrature direct digital down converter (DDD) is presented. The converter has a continuous time /spl Delta//spl Sigma/ noise shaping loopfilter with a quadrature bandpass characteristic. Through the integration of mixers in the AD converter, RF input signals in the range 0.3-1.6 GHz can be downconverted to a digital I and Q output stream at a bit rate of 128 MHz. The circuit is designed as a front-end for low power receivers with a 2 MHz wide IF bandwidth centered around 4 MHz. The converter, integrated in a 0.25 /spl mu/m CMOS technology, consumes 14 mW from a 2 V supply.

Optimization of a fully integrated low power CMOS GPS receiver

This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice level optimizations of simple building blocks and a full architecture optimization of the whole based on accurate models of the building blocks. The models of the building blocks are interpolated over the data points acquired in the Spice level simulations. The optimizer technique has been applied to the optimization of an architecture for a GPS receiver. The optimal design has been implemented in a standard 0.25μm CMOS process.