Martin Vogels

An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators

Circuit-level simulation of /spl Delta//spl Sigma/ modulators is a time-consuming task, taking one or more days for meaningful results. While there are a great variety of techniques and tools that speed up the simulations for discrete-time /spl Delta//spl Sigma/ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time counterpart. Nevertheless, in todays low-power, high-accuracy and/or very high-speed demands for A-to-D converters, designers are often forced to resort to the use of continuous-time /spl Delta//spl Sigma/ topologies. In this paper, we present a method for the high-level simulation of continuous-time /spl Delta//spl Sigma/ modulators as needed in top-down design and high-level modulator optimization. The method is based on analytical integration using behavioral models and exhibits the best tradeoff between accuracy, speed, and extensibility in comparison with other possible techniques that are reviewed briefly in this work. This methodology has been implemented in a user-friendly tool. Nonidealities such as finite gain, finite GBW, output impedance, and also nonlinearities, such as clipping, harmonic distortion, and the important effect of jitter are modeled. Finally, the tool was used to carry out some design-relevant experiments, illustrating the straightforward way of obtaining and exploring design tradeoffs at the modulator architectural level.

Architectural selection of A/D converters

A method for the architectural selection of analog to digital (A/D) converters based on a generic figure of merit is described. First a figure of merit for the power consumption is introduced. This figure of merit includes both target specifications and technology data and has five generic parameters. The values of these generic parameters can be estimated by analyzing the different converter structures or by means of a fitting procedure using data from published designs. It is shown that the generic parameters have different values for different types of converters. Therefore the tradeoff between speed, resolution, power dissipation and technology parameters depends on the type of converter. It is shown that the calculated figures of merit of the published designs, together with the calculated global trade-off comprise a surface in the (5 dimensional) design space. This surface makes it possible to accurately predict the power consumption and select the best converter solution for a certain target application. This can then serve as a first step in data converter synthesis or as a power estimator during high-level system design exploration.

A behavioral simulation tool for continuous-time ΔΣ modulators

Circuit--level simulation of ΔΣ modulators is a time--consuming task (taking one or more days for meaningful results). While there are a great variety of techniques and tools that speed up the simulations for discrete--time (DT) ΔΣ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous--time (CT) counterpart. Yet, in todays low--power, high--accuracy and/or very high--speed demands for A--to--D converters, designers are often forced to resort to the use of CT ΔΣ topologies. In this paper, we present a method for the high--level simulation of continuous--time ΔΣ modulators that is based on behavioral models and which exhibits the best trade--off between accuracy, speed and extensibility compared to other possible techniques that are reviewed briefly in this work. A user--friendly tool, implementing this methodology, is then presented. Nonidealities such as finite gain, finite GBW, output impedance and also nonlinearities such as clipping, harmonic distortion and the important effect of jitter are modeled. Finally, experiments were carried out using the tool, exploring important design trade--offs.

A behavioral simulation tool for continuous-time /spl Delta//spl Sigma/ modulators

Circuit-level simulation of /spl Delta//spl Sigma/ modulators is a time-consuming task (taking one or more days for meaningful results). While there are a great variety of techniques and tools that speed up the simulations for discrete-time (DT) /spl Delta//spl Sigma/ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time (CT) counterpart. Yet, in todays low-power, high-accuracy and/or very high-speed demands for A-to-D converters, designers are often forced to resort to the use of CT /spl Delta//spl Sigma/ topologies. In this paper, we present a method for the high-level simulation of continuous-time /spl Delta//spl Sigma/ modulators that is based on behavioral models and which exhibits the best trade-off between accuracy, speed and extensibility compared to other possible techniques that are reviewed briefly in this work. A user-friendly tool, implementing this methodology, is then presented. Nonidealities such as finite gain, finite GBW, output impedance and also nonlinearities such as clipping, harmonic distortion and the important effect of jitter are modeled. Finally, experiments were carried out using the tool, exploring important design trade-offs.

Dedicated system-level simulation of /spl Delta//spl Sigma/ modulators

A new approach is presented for significantly speeding up system-level simulation of /spl Delta//spl Sigma/ modulators. The method is based on high-level simulation that can be combined with an acceleration algorithm and has been implemented in C. Also, the decimator has been included yielding a complete and fast simulation of the whole converter. This reduces the bottleneck seen in system-level simulation of complete systems, e.g. receiver front-ends. Different topologies are included as well as the effects of most important nonidealities. Experimental results show the effectiveness of the approach.

Figure of Merit Based Selection of A/D Converters

A new method for selecting analog to digital (A/D) converters based on a generic figure of merit is described First a figure of merit is introduced that includes both specifications and technology data and that has five generic parameters. The values of these generic parameters can be found by means of a fitting procedure using data from published designs. It is shown that the generic parameters have different values for different types of converters. Therefore the trade-off between speed, resolution, power dissipation and technology parameters depends on the type of converter This trade-off can than be used to select a particular type of converter for a given application area.

Efficient analysis of the stability of sigma-delta modulators using wavelets

A new method is presented to efficiently estimate the stability boundary for sigma-delta modulators. Wavelet decomposition is used to cut up the input and output signals of the quantizer into different frequency portions. For the portion around the limit cycle an amplification factor and phase shift are calculated. This represents the transfer of the quantizer at that point. The so-formed linear system can then be analyzed using the phase margin. Only a small number of data points need to be evaluated making this method forty times faster than the traditional approach of long transient simulations, with only a very small error.

Efficient time-domain simulation of continuous-time /spl Delta//spl Sigma/ A/D converters using analytical integration

A novel approach to the simulation of continuous-time /spl Delta//spl Sigma/ modulators is presented. The proposed method uses analytical integration instead of numerical integration commonly used by SPICE-like simulators. First of all, expressions for a single integrator (which can be any integrator described by a second order model) are derived. These expressions allow one to calculate the states of the system at the next sampling event, using the states at the previous sampling event as initial conditions. Starting from these expressions recursive relations are derived for an (n+1)-th order /spl Delta//spl Sigma/ modulator. Since all derived expressions are in the time-domain, different forms of jitter can be implemented easily. To improve the simulator efficiency, all time-independent variables (i.e those that remain constant during a simulation) are calculated beforehand. The simulation method is implemented in C and experimental results show the method to be 20-30 times faster than a SPICE-like simulation of linear macromodels with a complexity comparable to the model used by the proposed method.

DAISY-CT: a high-level simulation tool for continuous-time /spl Delta//spl Sigma/ modulators

To reduce the long circuit-level simulation time of /spl Delta//spl Sigma/ modulators, a variety of techniques and tools exist that use high-level models for discrete-time (DT) /spl Delta//spl Sigma/ modulators. There is, however, no rigorous methodology implemented in a tool for the continuous-time (CT) counterpart. Therefore, we have developed a methodology for the high-level simulation of CT /spl Delta/E modulators and implemented this method in a user-friendly tool. Key features are the simulation speed, accuracy and extensibility. Nonidealities such as finite gain, finite GBW, output impedance and also the important effect of jitter are modelled. Finally, experiments were carried out using the tool, exploring important design trade-offs.

Systematic top-down design of A/D converters

In this paper, a systematic top-down design method for analog-to-digital converters is presented. Starting at a very high level, with only specifications for the DR, SNDR and bandwidth, the converter architecture is selected, followed by high level simulation. These results are then used in a building-block topology selection step, followed by an automatic sizing step and then intermediate and full transistor-level simulation. It is shown that the systematic flow can lead to faster and more robust design of ADCs, but that next to the top-down design flow a bottom-up modeling flow should be present.