Kenneth George Maclean

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC

This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10-9, and has a power consumption of 1.15 W for the core ADC.

A 610-mW zero-overhead class-G full-rate ADSL CO line driver

With the drive to increase the number of ports that can be incorporated onto a single linecard in an ADSL Central Office (CO), and the consequent power consumption and thermal management issues that this increased density raises, power dissipation is a key parameter in the design of an ADSL modem. This paper presents a full-rate ADSL CO line driver, consuming 610 mW through active termination and a zero-overhead class-G technique. The supply switching scheme used features very low overhead voltage, logic control, and controlled supply rail ramp rate, and requires analog signal peak prediction be done on the digital data stream. The process used features dielectrically isolated silicon-on-insulator 0.7-/spl mu/m complementary BiCMOS with thin-film resistors. The MOSFET class-G transistors operate in two modes for power efficiency and distortion control. The power consumption is 610 mW and the downstream missing tone power ratio is 69 dBC with 16-dB peak-to-average ratio support.

A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz

We show for the first time an 8.9 GS/s RF current-steering DAC, with an on-chip 1:1 Balun, and an 8-lane 12.5 Gbps JESD204B compliant SerDes, with a measured LTE ACPR >71 dBc in the adjacent 20 MHz band for a 2.9 GHz channel. The DAC has IM3 <;-65 dBc for output frequencies up to Nyquist. This performance is accomplished using a novel DAC switch driver and data/dummy-data scheme to minimize the pattern dependent sourcing/sinking of current on the DAC driver supply and ground. The DAC is fabricated in a 40nm dual-oxide CMOS process and dissipates 1.2W, with the contribution of the synthesized digital block and SerDes excluded.

A 610mW zero-overhead class G full-rate ADSL central-office line driver

A full-rate ADSL central-office line driver consumes 610mW through active termination and a zero-overhead class G technique. The supply switching scheme features very low overhead voltage, logic control, and controlled supply-rail ramp rate, and requires analog signal-peak prediction to be performed on the digital data stream.

A 12 bit 1.6 GS/s BiCMOS 2×2 hierarchical time-interleaved pipeline ADC

A 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process is presented. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T/H to improve the dynamic performance of the individual sub-ADCs and to reduce both the complexity of the required interleaving background calibration algorithms and the error rate. It achieves an SFDR of 79 dBc at low frequency inputs and 66 dBc at Nyquist, and has an error rate of less than 10-9.