Kensuke Ishikawa

Suppression of stress-induced voiding in copper interconnects

Studied stress-induced voiding in Cu interconnects in the temperature range below 250/spl deg/C, and found two different voiding modes. One mode occurs inside a via having wide wire above it, and can be suppressed by optimizing the via shape and the via-cleaning process. The other mode occurs under a via having wide wire below it and can be suppressed by increasing the Cu grain size and improving the adhesion of the barrier metal with Cu.

Process and reliability of air-gap Cu interconnect using 90-nm node technology

A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.

Observation of microstructures in the longitudinal direction of very narrow Cu interconnects

We have succeeded in observing the longitudinal microstructure of very narrow Cu interconnects for the first time. We found that the average grain sizes along the longitudinal direction of Cu interconnect trenches increased with increasing line width, and they were 278 nm for 80 nm, 303 nm for 100 nm, and 346 nm for 180 nm wide interconnects. Ratios of the average grain size to line width were 3.5 for 80 nm, 3.03 for 100 nm, and 1.9 for 180 nm line widths.

A reliability study of barrier-metal-clad copper interconnects with self-aligned metallic caps

An advanced interconnection technology was studied by evaluating the performance of copper (Cu) interconnections capped with a barrier metal. Good selectivity of self-aligned tungsten (W) caps grown by chemical vapor deposition was obtained, and the isolation resistance and leakage current between adjacent Cu interconnects capped with W were similar to those between conventional Cu interconnects. There were also no significant wiring resistance or via resistance differences of between W-capped Cu interconnects and conventional Cu interconnects. When two-level Cu interconnects were fabricated to check the effects of the undulation of the interlayer dielectric deposited on W-capped Metal-1 lines, good isolation of fine-pitch Metal-2 lines was obtained. The reliability of metal-capped structures was evaluated by measuring time-dependent dielectric breakdown (TDDB), electromigration, and stressmigration. The TDDB lifetime of adjacent W-capped Cu interconnects 0.15 /spl mu/m apart was found to be at least as long as that of conventional Cu interconnects with the same spacing, and the electromigration lifetime of W-capped Cu interconnects was found to be superior to that of conventional Cu interconnects. Furthermore, self-aligned caps of W or cobalt tungsten boron were found to suppress the stress-induced voiding of Cu interconnects.

Simple self-aligned air-gap interconnect process with Cu/FSG structure

A novel self-aligned air-gap interconnect process with Cu/FSG structure was proposed. The key feature is the use of an easily removal sacrifice film by dry-etching process with a reducing gas. This process consists of a conventional Cu damascene process with 130 nm node CMOS technology. In this study, a 2 level Cu interconnect was fabricated and the effective dielectric constant of 2.3/spl sim/2.6 has been successfully achieved. These are consistent with the capacitance reduction by 37/spl sim/41% compared with a conventional Cu/FSG structure.

Reliability of air-gap Cu interconnect and approach to selective W sealing using 90nm node technology

4 levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the air-gap interconnects using ArF/90nm node technology was investigated. There are distinguished improvements of leakage current and TDDB characteristics by the application of air-gap interconnects. In addition, an air-gap interconnect is improved with a selective W sealing process . This results in drastic reduction of capacitance and effective dielectric constant.

Integration and reliability of Cu-SiOC interconnect for ArF/90-nm node CMOS technology

Cu-SiOC interconnects for ArF/90-nm node technology were investigated. This paper describes the integration and reliability issues. The methods to improve chemical mechanical polishing delamination, SiOC damage and electrical shorts through the bottom interface of Cu interconnects were discussed. Reliability characteristics, such as stress-migration, electro-migration, and time-dependent dielectric breakdown (TDDB) were studied. Cu diffusion with via resistance increase by high-temperature stress, and TDDB degradation due to the ArF process were found. It was confirmed that the suggested integration process was mature and sufficiently reliable for normal operating conditions.

Integration and reliability issues of Cu/SiOC interconnect for ArF/90 nm node SoC manufacturing

Cu/SiOC interconnect technology for ArF/90 nm node SoC manufacturing was investigated. This paper describes the integration and reliability issues. With regard to integration technologies, CMP delamination, SiOC damage and short defects on the trench bottom were improved dramatically. As to reliabilities, SM (stress migration), EM (electromigration) and TDDB (time dependent dielectric breakdown) were studied. Cu diffusion with via resistance increase by high temperature stress, and TDDB degradation due to the ArF process were found. It was confirmed that the suggested integrated process was mature and sufficiently reliable for the operation condition.

Impact of metal deposition process upon reliability of dual-damascene copper interconnects

In this paper, we discuss the effect of adhesion strength between TaN/Ta barrier and copper (Cu) upon the reliability of dual-damascene Cu interconnects as well as the effect of stepcoverage. The ionized metal bias sputtering (IMBS) method was applied to TaN/Ta barrier and Cu seed formation of 0.13 /spl mu/m-node dual-damascene Cu interconnects and the electromigration and stress migration characteristics were successfully improved.

A robust, deep-submicron copper interconnect structure using self-aligned metal capping method

A high reliable copper interconnects with metallic cap is studied. W-CVD process combined with pre-cleaning succeeded in self-aligned metal deposition on Cu interconnects surface. Degradation of leakage current between adjacent Cu wires is suppressed by process optimization. Reliability characteristics such as electromigration and stress-migration of metal capped Cu interconnect structure are investigated and are superior to those of conventional one. These results reveal that Cu and vacancy diffusion at the Cu wire surface is successfully suppressed by eliminating Cu/dielectric interface.