Kiyohiko Sato

Process and reliability of air-gap Cu interconnect using 90-nm node technology

A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.

Simple self-aligned air-gap interconnect process with Cu/FSG structure

A novel self-aligned air-gap interconnect process with Cu/FSG structure was proposed. The key feature is the use of an easily removal sacrifice film by dry-etching process with a reducing gas. This process consists of a conventional Cu damascene process with 130 nm node CMOS technology. In this study, a 2 level Cu interconnect was fabricated and the effective dielectric constant of 2.3/spl sim/2.6 has been successfully achieved. These are consistent with the capacitance reduction by 37/spl sim/41% compared with a conventional Cu/FSG structure.

Multilevel Interconnect With Air-Gap Structure for Next-Generation Interconnections

A misalignment-free multilevel air-gap interconnect with a via-base structure was fabricated by self-aligned gap formation and etch back. Its reliability was investigated by measuring stress-induced voiding, electromigration (EM), and time-dependent dielectric breakdown (TDDB). There was no via degradation after thermal stress (at 200degC for 500 h). The EM lifetime was the same as that of a conventional damascene interconnect, and the TDDB lifetime was about two orders of magnitude longer. Increasing the etch-back thickness of the interlayer dielectric increased the capacitance reduction by about 17%-32%. The frequency of a ring oscillator with an air-gap interconnect was higher by 17% on average than that with a conventional damascene interconnect. The simulation results demonstrate that this air-gap interconnect has the effective dielectric constant required for next-generation interconnects (22-nm node).

Dual damascene process for air-gap Cu interconnects using conventional CVD films as sacrificial layers

A dual damascene Cu air-gap interconnect was investigated. To solve issues such as cost and electrical shorts from CMP scratches, a conventional CVD film was used as a sacrificial layer instead of the SOD film that we reported previously. The process integration, electrical characteristics and the TDDB reliability were discussed. The TDDB lifetime was drastically improved, and 4 levels of dual damascene Cu interconnects were successfully fabricated.

Reliability of air-gap Cu interconnect and approach to selective W sealing using 90nm node technology

4 levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the air-gap interconnects using ArF/90nm node technology was investigated. There are distinguished improvements of leakage current and TDDB characteristics by the application of air-gap interconnects. In addition, an air-gap interconnect is improved with a selective W sealing process . This results in drastic reduction of capacitance and effective dielectric constant.

Integration and reliability of Cu-SiOC interconnect for ArF/90-nm node CMOS technology

Cu-SiOC interconnects for ArF/90-nm node technology were investigated. This paper describes the integration and reliability issues. The methods to improve chemical mechanical polishing delamination, SiOC damage and electrical shorts through the bottom interface of Cu interconnects were discussed. Reliability characteristics, such as stress-migration, electro-migration, and time-dependent dielectric breakdown (TDDB) were studied. Cu diffusion with via resistance increase by high-temperature stress, and TDDB degradation due to the ArF process were found. It was confirmed that the suggested integration process was mature and sufficiently reliable for normal operating conditions.

Integration and reliability issues of Cu/SiOC interconnect for ArF/90 nm node SoC manufacturing

Cu/SiOC interconnect technology for ArF/90 nm node SoC manufacturing was investigated. This paper describes the integration and reliability issues. With regard to integration technologies, CMP delamination, SiOC damage and short defects on the trench bottom were improved dramatically. As to reliabilities, SM (stress migration), EM (electromigration) and TDDB (time dependent dielectric breakdown) were studied. Cu diffusion with via resistance increase by high temperature stress, and TDDB degradation due to the ArF process were found. It was confirmed that the suggested integrated process was mature and sufficiently reliable for the operation condition.