Tatsuyuki Saito

Impact of low-k dielectrics and barrier metals on TDDB lifetime of Cu interconnects

Time-dependent dielectric breakdown (TDDB) in Cu metallization and the dependence on the presence of barrier metal, barrier metal thickness, the kind of barrier metals and the low-k dielectrics, is investigated. There is a distinct difference in TDDB degradation mechanism with and without barrier metals. TDDB degradation of Cu interconnects without and with barrier metal is caused by bulk mode and CMP-surface mode, respectively. The TDDB characteristics with barrier metal are almost the same for different barrier metal thicknesses and depends much more strongly on the electric field strength than the MIS structure. Additionally, both degradations, related to Cu-ion diffusion, are mainly caused not by thermal stress but by electrical stress. The barrier properties of Ta and TaN are better than those of TiN against Cu-ion diffusion into dielectrics, for TDDB. In the case of a low-k structure, TDDB properties with barrier metal also depend on the CMP-surface. With low-k dielectrics, the electric field strength is concentrated near the CMP surface and the TDDB lifetime reduces as the k-value decreases. However, all low-k structures in this study are able to satisfy the 10-year TDDB reliability specifications for the capacitor.

Suppression of stress-induced voiding in copper interconnects

Studied stress-induced voiding in Cu interconnects in the temperature range below 250/spl deg/C, and found two different voiding modes. One mode occurs inside a via having wide wire above it, and can be suppressed by optimizing the via shape and the via-cleaning process. The other mode occurs under a via having wide wire below it and can be suppressed by increasing the Cu grain size and improving the adhesion of the barrier metal with Cu.

A novel copper interconnection technology using self aligned metal capping method

A self aligned metal capping process for Copper damascene interconnect is newly developed in this study. A tungsten capping layer is selectively formed on the Cu interconnect using the preferential deposition phenomenon of W-CVD assisted by pre and post treatment. This technology is applied to 0.2 /spl mu/m bipolar-CMOS LSI with multilevel Cu interconnects, and then yield, reliability and operation speed are evaluated.

Improvement of thermal stability of via resistance in dual damascene copper interconnection

Thermal stability of via resistance in the multilevel dual damascene Cu interconnection was investigated. The via resistance stability strongly depends on via size, via density and width of connecting Cu wires. The significant via-resistance shift was introduced by stress-induced voiding. To avoid the voiding failure, optimization of heat treatments after electroplating (EP)-Cu deposition are necessary for both stability of Cu films and adhesion of barrier layer with Cu. Thermal stress balance between Cu wires and inter-level-dielectric (ILD) is also important to suppress the via degradation. The dual damascene structure with lower-stress and lower-Youngs modulus ILD films such as FSG can provide wider process windows for the stability of the via resistance.

Process and reliability of air-gap Cu interconnect using 90-nm node technology

A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.

A 0.2-/spl mu/m bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors

A 0.2-/spl mu/m bipolar-CMOS process technology on a bonded SOI wafer was developed for ultra-high-speed applications. This process was used to fabricate a new cache memory chip consisting of 9-Mb 0.6-ns SRAMs and a 200-K 25-ps ECL gate array. To achieve high performance, the 0.2-/spl mu/m bipolar-CMOS process features a 6-/spl mu/m/sup 2/-cell-size BJT with a 50-nm base width, a 6T-CMOS memory cell and copper interconnects that reduce wiring delay by 30%. A combination of low-energy ion-implantation and two-step annealing was applied to form a low-leakage, shallow base junction. A bonded SOI wafer with deep and shallow trench isolations was used to maximize the BJT performance.

Observation of microstructures in the longitudinal direction of very narrow Cu interconnects

We have succeeded in observing the longitudinal microstructure of very narrow Cu interconnects for the first time. We found that the average grain sizes along the longitudinal direction of Cu interconnect trenches increased with increasing line width, and they were 278 nm for 80 nm, 303 nm for 100 nm, and 346 nm for 180 nm wide interconnects. Ratios of the average grain size to line width were 3.5 for 80 nm, 3.03 for 100 nm, and 1.9 for 180 nm line widths.

A reliability study of barrier-metal-clad copper interconnects with self-aligned metallic caps

An advanced interconnection technology was studied by evaluating the performance of copper (Cu) interconnections capped with a barrier metal. Good selectivity of self-aligned tungsten (W) caps grown by chemical vapor deposition was obtained, and the isolation resistance and leakage current between adjacent Cu interconnects capped with W were similar to those between conventional Cu interconnects. There were also no significant wiring resistance or via resistance differences of between W-capped Cu interconnects and conventional Cu interconnects. When two-level Cu interconnects were fabricated to check the effects of the undulation of the interlayer dielectric deposited on W-capped Metal-1 lines, good isolation of fine-pitch Metal-2 lines was obtained. The reliability of metal-capped structures was evaluated by measuring time-dependent dielectric breakdown (TDDB), electromigration, and stressmigration. The TDDB lifetime of adjacent W-capped Cu interconnects 0.15 /spl mu/m apart was found to be at least as long as that of conventional Cu interconnects with the same spacing, and the electromigration lifetime of W-capped Cu interconnects was found to be superior to that of conventional Cu interconnects. Furthermore, self-aligned caps of W or cobalt tungsten boron were found to suppress the stress-induced voiding of Cu interconnects.

Simple self-aligned air-gap interconnect process with Cu/FSG structure

A novel self-aligned air-gap interconnect process with Cu/FSG structure was proposed. The key feature is the use of an easily removal sacrifice film by dry-etching process with a reducing gas. This process consists of a conventional Cu damascene process with 130 nm node CMOS technology. In this study, a 2 level Cu interconnect was fabricated and the effective dielectric constant of 2.3/spl sim/2.6 has been successfully achieved. These are consistent with the capacitance reduction by 37/spl sim/41% compared with a conventional Cu/FSG structure.

Dual damascene process for air-gap Cu interconnects using conventional CVD films as sacrificial layers

A dual damascene Cu air-gap interconnect was investigated. To solve issues such as cost and electrical shorts from CMP scratches, a conventional CVD film was used as a sacrificial layer instead of the SOD film that we reported previously. The process integration, electrical characteristics and the TDDB reliability were discussed. The TDDB lifetime was drastically improved, and 4 levels of dual damascene Cu interconnects were successfully fabricated.