Kenzo Manabe

Dual workfunction Ni-Silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices

We present a new threshold-voltage (Vth) control technique for fully-silicided (FUSI) metal/high-k gate stacks which are suitable for 45nm-node LOP and LSTP CMOS. The key is the phase control of FUSI Ni-silicide by changing Ni film thickness prior to silicidation anneal. As a result, Ni/sub 3/Si and NiSi/sub 2/ are formed whose effective workfunctions (WFs) on HfSiON are found to be 4.8eV and 4.4eV, respectively, being largely displaced from Si-midgap by /spl plusmn/0.2eV. Meanwhile, the dopant segregation method, known to be successful in Vth-control of NiSi on SiO/sub 2/, did not work on HfSiON. With Ni/sub 3/Si-PMOS and NiSi/sub 2/-NMOS transistors, a wide range of Vth-tuning is achieved coping with both LSTP and LOP requirements. At the same time, leakage suppression merit is better than the 45nm-node targets at electrical thickness (Tinv) around 2.0 nm. Also, our phase-controlled fully silicided (PC-FUSI) devices show excellent mobility characteristics.

Electronic structure analysis of Zr silicate and Hf silicate films by using spatially resolved valence electron energy-loss spectroscopy

Electronic structures near the band gaps of Zr silicate and Hf silicate thin films were investigated experimentally and theoretically. We show that the electronic structure of Zr silicate can be reproduced by a superposition of the electronic structures of ZrO2 and SiO2. Similarly, the electronic structure of Hf silicate can be reproduced by a superposition of the electronic structures of HfO2 and SiO2. This indicates that, in these silicates, the lowest conduction band states are composed mostly of d states of Zr or Hf, and the valence band states mostly of O 2p states. The similarity of the electronic structures of these silicates can be attributed to the similarity of the chemical natures of Zr and Hf atoms. Consequently, when these silicate films are used as gate dielectrics in metal–oxide–semiconductor transistors, the gate leakage current could be strongly affected by d states of Zr or Hf.

Highly reliable HfSiON CMOSFET with phase controlled NiSi (NFET) and Ni/sub 3/Si (PFET) FUSI gate electrode

We have clarified that the Ni/Si composition of gate electrode and Hf/Si composition of HfSiON gate insulator are the important parameter to obtain suitable Vth of CMOS. The amount of Hf-Si bonds at the gate/insulator interface is key parameter to control Fermi-level pinning effect. The crystalline phase controlled full Ni-silicide gate (PC-FUSI) and 50% Hf composition HfSiON realize suitable Vth=+/-0.5V with tight distribution. Performance improvement (NFET:1.28 times and PFET:1.52 times) of PC-FUSI FET was also confirmed against poly-Si gate FET with keeping low leakage current. Sufficient long term reliability was also demonstrated through BT stress evaluation.

High-Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics

Dual metal gate transistors with high-k gate dielectrics have been investigated for low-power metal oxide semiconductor (MOS) devices in 45 nm nodes and beyond. Using high-quality HfSiO gate dielectrics, using TiN and Ta for the gate electrode, and minimizing process damage, we have succeeded in markedly improving device performance. Effective work functions of 4.9 eV for TiN and 4.3 eV for Ta on HfSiO were obtained for the first time. Symmetrical threshold voltages of ±0.5 V were realized for these work functions. Small hysteresis and low interface trap densities for both TiN and Ta were obtained, which are almost the same as those of poly-Si/HfSiON transistors. No degradation in electron mobility was achieved for the first time for Ta-NMOS transistors at an effective field of 1.0 MV/cm. The gate leakage current at an equivalent electrical oxide thickness in an inversion of 1.7 nm was suppressed to 1 mA/cm-2 at a gate bias of Vth+0.6 V.

Spatially-resolved valence-electron energy-loss spectroscopy of Zr-oxide and Zr-silicate films

We examined electronic structures in Zr-oxide (ZrO2) and Zr-silicate (ZrxSi1−xO2) films deposited on Si substrates by using valence-electron energy-loss spectroscopy combined with scanning transmission electron microscopy (the electron probe diameter was about 0.3 nm). Our analysis indicated that both valence-electron excitations in ZrO2 and in SiO2 occurred in the ZrxSi1−xO2 films. Therefore, the band gaps in the ZrxSi1−xO2 films should be dominated by an energy gap between O 2p and Zr 4d states.

Analysis of Origin of Threshold Voltage Change Induced by Impurity in Fully Silicided NiSi/SiO2 Gate Stacks

To investigate the origin of the threshold voltage (Vth) change by impurity segregation in a fully silicided (FUSI) NiSi/SiO2 gate stack, for the first time we directly examined the vacuum work function (vac) of the electrodes, the electrical dipole moment (Dinter), and the chemical state of the impurity at the NiSi/SiO2 interface by backside X-ray photoelectron spectroscopy (XPS). We found that the impurity causes neither a change in the vac nor the formation of a fixed charge in SiO2, and that the interface dipole is a dominant factor to cause the Vth change. We propose that the origin of the interface dipole is the impurity atoms with large electronegativity bonded to both NiSi and SiO2 at the NiSi/SiO2 interface.

Mechanism for Leakage Reduction by La Incorporation in a

In this letter, we investigated a dominant mechanism for leakage reduction by the incorporation of La in a HfO2/SiO2 gate stack. We compared the experimental data for the leakage current for the La-doped HfO2/SiO2 gate stack and the calculation for tunnel current through the gate stack, assuming that the La-induced dipole increases the barrier height of HfO2 for electrons from the substrate. The agreement between the experimental data and calculated values strongly suggests that the main cause for leakage reduction is the effective barrier height modulation induced by the interface dipole.

\hbox{HfO}_{2}\hbox{/SiO}_{2}\hbox{/Si}

The fully silicided (FUSI)-nickel monosilicide (NiSi) metal gate electrode on the HfSiON gate dielectric has been investigated for low-power metal-oxide-semiconductor field effect transistors (MOSFETs). We found that the FUSI-NiSi electrode on the HfSiON dielectric has a work function of 4.55 eV, which improved the threshold voltage shift of PMOSFETs by 0.15 V compared with that of the poly-Si/HfSiON MOSFETs. At the same time, full silicidation eliminated the gate depletion and thereby we achieved the capacitance equivalent thickness at inversion of 2.1 nm and a five-order-of-magnitude reduction in the gate leakage current compared with the poly-Si/SiO2 devices. Moreover, we obtained an excellent carrier mobility for the FUSI-NiSi/HfSiON transistors (PMOS: 100%, NMOS: 90% compared with the poly-Si/SiO2 reference transistors). These results show that the FUSI-NiSi/HfSiON gate stack is a promising candidate for next-generation low-power MOSFETs.

Gate Stack

We have developed a novel nickel self-aligned silicide (salicide) process for future scaled metal-oxide-semiconductor field-effect transistors (MOS-FETs). Ni/Si multi-layered structures were fabricated by the cyclic deposition of Ni and Si. Nickel monosilicide (NiSi) films with a low resistivity, a uniform thickness, and a good morphology were obtained on Si(100) substrates after annealing at 400–600°C. Nickel silicide formed on SiO2 can be removed by wet etching if the total atomic number ratio of Ni to Si in the deposited layers is larger than unity. This shows that the nickel salicide process is possible by our method. We have fabricated MOS-FET structures with NiSi and confirmed that the consumption of Si in the substrate is much lower in our method than in the conventional method.

Fully silicided NiSi gate electrodes on HfSiON gate dielectrics for low-power applications

We demonstrate midgap and band-edge effective workfunctions (EWFs) control with simple metal gate process scheme (single metal gate/single gate dielectric), using impurity-segregated NiSi2/SiON structure for embedded memory application. The application of midgap and band-edge EWF enables us to lower power consumption in SRAM and logic devices by 30% and 15% compared to poly-Si devices, respectively, due to reduced channel impurity concentration, suppressed gate depletion and high carrier mobility. These results show that NiSi2/SiON stack is one of the most promising candidates for future system on chip (SoC) devices with embedded memory.