Makiko Oshida

Suppression of lateral charge redistribution using advanced impurity trap memory for improving high temperature retention

For retention improvement in scaled SONOS-type nonvolatile memory, deep traps with controllable density were formed by adding metal impurities into gate oxide. We find that Ti additives create deep traps in silicon dioxide, with high electron capture efficiency Charge storage node changed from TiO2 floating-gate (15Aring) to nano-crystals (3Aring), and further to atomic-sized traps (0.4Aring) by decreasing Ti amount. Discrete atomic-sized traps successfully suppressed lateral charge redistribution, improving retention at 150degC

Electron Holography Characterization of Ultra Shallow Junctions in 30-nm-Gate-Length Metal–Oxide–Semiconductor Field-Effect Transistors

We demonstrate that electron holography can be used to map the electrostatic potential in source–drain extensions (SDEs) of 30-nm-gate-length metal–oxide–semiconductor field-effect transistors (MOSFETs). To reduce specimen-preparation artifacts, which have prevented the electron holography of advanced MOSFETs, we prepared specimens using low-energy backside Ar ion milling. Our analysis revealed the potential distributions in SDEs formed by a co-implantation technique and those formed by a conventional BF2 implantation technique and showed that the potential change at the p–n junctions is more abrupt in the former. We also show that our electron holography results clearly describe the roll-off characteristics of the MOSFETs.

Analysis of Origin of Threshold Voltage Change Induced by Impurity in Fully Silicided NiSi/SiO2 Gate Stacks

To investigate the origin of the threshold voltage (Vth) change by impurity segregation in a fully silicided (FUSI) NiSi/SiO2 gate stack, for the first time we directly examined the vacuum work function (vac) of the electrodes, the electrical dipole moment (Dinter), and the chemical state of the impurity at the NiSi/SiO2 interface by backside X-ray photoelectron spectroscopy (XPS). We found that the impurity causes neither a change in the vac nor the formation of a fixed charge in SiO2, and that the interface dipole is a dominant factor to cause the Vth change. We propose that the origin of the interface dipole is the impurity atoms with large electronegativity bonded to both NiSi and SiO2 at the NiSi/SiO2 interface.

Strain Controlled CMOSFET with Phase Controlled Full-Silicide (PC-FUSI)/HfSiON Gate Stack Structure for 45nm-node LSTP Devices

By using Ni-FUSI/HfSiON gate structure with NiSi electrode for NFET and Ni₃Si for PFET, excellent T_inv-I_g property (T_inv:1.8 nm , I_g:7E-3 A/cm²), symmetrical V_th (+/-0.4V), high I_on:510/270 muA/mum with I_off: 100 pA/mum are achieved at L_g:45nm. These properties are suitable for 45nm-node CMOSFET for LSTP. To introduce Ni₃Si electrode for PFET, poly-Si gate electrode height optimization successfully overcomes volume expansion problem which causes Ni diffusion into Si substrate during full-silicidation process. For the precise thickness control of thin poly-Si electrode, we propose four-layered gate stack process. Channel strain measurement reveals that Ni₃Si from thin poly-Si introduces compressive strain to channel, which increases the hole mobility. It is considered that the thermal expansion coefficient mismatch between Ni₃Si and Si realizes the compressive stress compensating the tensile stress induced during silicidation. TEM observation shows connecting point between NiSi of NFET and Ni₃Si of PFET has abrupt interface, which suggests phase controlled full-silicidation (PC-FUSI) process is suitable for the further scaling down of CMOSFET for LSTP

Impact of Crystalline Phase of Ni-Full-Silicide Gate Electrode on TDDB Reliability of HfSiON Gate Stacks

We investigated the influences of gate metals (poly-Si, NiSi, Ni 3Si) on the time dependent dielectric breakdown (TDDB) reliability of phase-controlled Ni-full-silicide/HfSiON n-FETs. The TDDB reliability of the NiSi-electrode FETs was comparable to that of poly-Si-electrode FETs. However, the reliability was degraded by further Ni-enriching to Ni3Si. We presume that the degradation of the base SiO2 layer is responsible for this. We do not relate the TDDB degradation to Ni diffusion into the insulator, but rather to the strain that is higher in Ni3Si samples

Formation of Nickel Self-Aligned Silicide by Using Cyclic Deposition Method

We have developed a novel nickel self-aligned silicide (salicide) process for future scaled metal-oxide-semiconductor field-effect transistors (MOS-FETs). Ni/Si multi-layered structures were fabricated by the cyclic deposition of Ni and Si. Nickel monosilicide (NiSi) films with a low resistivity, a uniform thickness, and a good morphology were obtained on Si(100) substrates after annealing at 400–600°C. Nickel silicide formed on SiO2 can be removed by wet etching if the total atomic number ratio of Ni to Si in the deposited layers is larger than unity. This shows that the nickel salicide process is possible by our method. We have fabricated MOS-FET structures with NiSi and confirmed that the consumption of Si in the substrate is much lower in our method than in the conventional method.

Electron Holography Characterization of Ultra-Shallow Junctions in 30-nm Gate-length MOS-FETs

in 30-nm Gate-length MOS-FETs Nobuyuki Ikarashi, Makiko Oshida, Makoto Miyamura, Motofumi Saitoh, Akira Mineji, and Seiichi Shishiguchi NEC Corporation, Device Platforms Research Laboratories, 1120 Shimokuzawa, Sagamihara, 229-1198, Japan Phone: +81-42-771-2458 E-mail: n-ikarashi@cq.jp.nec.com 2 NEC Electronics Corporation, Process Technology Division, 1120 Shimokuzawa, Sagamihara, 229-1198, Japan

Practical Vth Control Methods for Ni-FUSI/HfSiON MOSFETs on SOI Substrates

The methods for controlling threshold voltage (Vth) of Ni-fully-silicide (Ni-FUSI)/HfSiON CMOSFETs on SOI substrates were investigated. We achieved the suitable Vth for both low standby power (LSTP) and low operation power (LOP) devices by using the adjustment of channel doping for NFETs with NiSi gate electrode and the phase controlled (PC) Ni-FUSI technique for PFETs. We also investigated the Vth control by implantation of F and N. Applying the F-implantation technique to Ni-FUSI/HfSiON CMOSFETs on SOI substrates has the possibility to realize Vth control for both LSTP and LOP devices by single phase Ni-FUSI (NiSi) gate electrode