Takuya Yoshihara

Dual workfunction Ni-Silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices

We present a new threshold-voltage (Vth) control technique for fully-silicided (FUSI) metal/high-k gate stacks which are suitable for 45nm-node LOP and LSTP CMOS. The key is the phase control of FUSI Ni-silicide by changing Ni film thickness prior to silicidation anneal. As a result, Ni/sub 3/Si and NiSi/sub 2/ are formed whose effective workfunctions (WFs) on HfSiON are found to be 4.8eV and 4.4eV, respectively, being largely displaced from Si-midgap by /spl plusmn/0.2eV. Meanwhile, the dopant segregation method, known to be successful in Vth-control of NiSi on SiO/sub 2/, did not work on HfSiON. With Ni/sub 3/Si-PMOS and NiSi/sub 2/-NMOS transistors, a wide range of Vth-tuning is achieved coping with both LSTP and LOP requirements. At the same time, leakage suppression merit is better than the 45nm-node targets at electrical thickness (Tinv) around 2.0 nm. Also, our phase-controlled fully silicided (PC-FUSI) devices show excellent mobility characteristics.

Variation of internal stresses in sputtered Ta films

It has been found that the stress of a sputtered Ta film gradually changes toward compression in a normal atmosphere. It was found that the cause of this Ta film stress change is quick oxygen diffusion along grain boundaries. The amount of this stress change was measured to be about ∼3×107 N/m2 when the Ta film was sputtered with Ar gas below 3.5 Pa. The stress change occurred neither in a vacuum nor in a nitrogen atmosphere, but only in an oxygen atmosphere. Once the Ta films had been annealed for 60 min at 100 °C in an oxygen atmosphere, no further stress change was observed.

High-Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics

Dual metal gate transistors with high-k gate dielectrics have been investigated for low-power metal oxide semiconductor (MOS) devices in 45 nm nodes and beyond. Using high-quality HfSiO gate dielectrics, using TiN and Ta for the gate electrode, and minimizing process damage, we have succeeded in markedly improving device performance. Effective work functions of 4.9 eV for TiN and 4.3 eV for Ta on HfSiO were obtained for the first time. Symmetrical threshold voltages of ±0.5 V were realized for these work functions. Small hysteresis and low interface trap densities for both TiN and Ta were obtained, which are almost the same as those of poly-Si/HfSiON transistors. No degradation in electron mobility was achieved for the first time for Ta-NMOS transistors at an effective field of 1.0 MV/cm. The gate leakage current at an equivalent electrical oxide thickness in an inversion of 1.7 nm was suppressed to 1 mA/cm-2 at a gate bias of Vth+0.6 V.

Low-stress sputtered chromium–nitride hardmasks for x-ray mask fabrication

We have developed low-stress chromium nitride (CrN) films as hardmasks for x-ray absorber etching. The stress in the CrN films is 3 MPa and its distribution (gradient) is less than 10 MPa in a 25×25 mm area. In addition, the CrN film is electrically conductive (1.4 Ω/□). We have fabricated 0.10 μm line-and-space patterns in 0.4-μm-thick tantalum germanide using a 75-nm-thick CrN hardmask. The results demonstrate that a sputtered CrN film is an excellent hardmask material for x-ray mask fabrication.

X-Ray Mask Distortion Induced in Back-Etching Preceding Subtractive Fabrication: Resist and Absorber Stress Effect

The influence of resist and absorber stress distributions on X-ray mask distortion induced during back-etching preceding subtractive fabrication is analyzed experimentally and simulated. The stress distribution (gradient) in a resist and/or that in an absorber film causes larger pattern displacement rather than the film average stress. Some resists have considerably high stress after coating on a wafer, and this stress also changes during exposure, causing local pattern displacements. However, use of chemically amplified resist systems, in which the reaction after exposure is limited to a small amount acid generation, might solve this problem. Low-stress positive-tone resists should thus be developed.

Sputtered TaX film properties for x‐ray mask absorbers

The characteristics of several elements for binary tantalum alloys, such as crystal structure, x‐ray absorption, and dry‐etching properties were systematically investigated. As a result, TaGe, TaSi, TaRe, and TaTi were selected as potential candidates for x‐ray mask absorbers. We deposited these Ta alloys using conventional magnetron sputtering. The stress in the TaX films was controlled more precisely than in Ta films. It was found that TaGe was one of the most suitable materials based on x‐ray absorption, stress control, and fine pattern fabrication.

Sputtering of fibrous‐structured low‐stress Ta films for x‐ray masks

In order to achieve precise control for the internal stress of x‐ray absorber films, we have controlled the sputtering‐gas (Xe) pressure within ±0.002 Pa (at 0.5 Pa) using a newly developed ultrahigh‐vacuum sputtering system, but we found that it was difficult to reproducibly obtain sufficiently low‐stress Ta films over the long term. We therefore investigated the relationship between the internal stress and substrate temperature at a low deposition pressure (0.45 Pa). It was found that internal stress changes basically toward tensile with increasing substrate temperature because of the bimetal effect, but at substrate temperature from 205 to 220 °C, the internal stress changes toward compressive with increasing temperature. We characterized Ta films deposited at various temperatures using x‐ray diffraction and secondary electron microscopy and found that a film deposited at 205 °C was columnar‐structure β‐Ta and that one deposited at 240 °C was fibrous‐structured β‐Ta. Films deposited at temperatures higher than 270 °C were rough‐surfaced α‐Ta. For films deposited at pressures lower than 0.8 Pa and at a substrate temperature of 240 °C, the internal stress was almost constant regardless of gas pressure fluctuation. Thus, at 240 °C and 0.45 Pa, we can deposit low‐stress (<5×107 N/m2) Ta films with excellent long‐term reproducibility.

Fully silicided NiSi gate electrodes on HfSiON gate dielectrics for low-power applications

The fully silicided (FUSI)-nickel monosilicide (NiSi) metal gate electrode on the HfSiON gate dielectric has been investigated for low-power metal-oxide-semiconductor field effect transistors (MOSFETs). We found that the FUSI-NiSi electrode on the HfSiON dielectric has a work function of 4.55 eV, which improved the threshold voltage shift of PMOSFETs by 0.15 V compared with that of the poly-Si/HfSiON MOSFETs. At the same time, full silicidation eliminated the gate depletion and thereby we achieved the capacitance equivalent thickness at inversion of 2.1 nm and a five-order-of-magnitude reduction in the gate leakage current compared with the poly-Si/SiO2 devices. Moreover, we obtained an excellent carrier mobility for the FUSI-NiSi/HfSiON transistors (PMOS: 100%, NMOS: 90% compared with the poly-Si/SiO2 reference transistors). These results show that the FUSI-NiSi/HfSiON gate stack is a promising candidate for next-generation low-power MOSFETs.

Applicability test for synchrotron radiation x‐ray lithography in 64‐Mb dynamic random access memory fabrication processes

To evaluate the applicability of synchrotron radiation x‐ray lithography (SRXL) in ultra‐large‐scale integration manufacturing processes, we simulate a part of a dynamic random access memory process using SRXL. Four levels of x‐ray masks (field, gate, bit contact, and bit line), including fiducial patterns for coordinate/overlay measurement, alignment marks, and 0.4‐μm‐rule memory cells were fabricated using an i‐line stepper. The maximum overlay error between the different level masks was 60–100 nm. In SRXL processes alignment errors of the x‐ray stepper were 60–100 nm (3σ), and the overlay errors over a 20‐mm‐exposure field were 130–160 nm (‖mean‖+3σ) in most of alignment levels. Critical dimension control of 27–47 nm was obtained for gate length and contact hole diameter.

Sub‐half‐micron metal–oxide–semiconductor device fabrication using a compact synchrotron radiation lithography system

In order to evaluate the usefulness of the compact synchrotron radiation (SR) lithography system using a superconducting synchrotron light source ‘‘AURORA,’’ sub‐half‐micron metal–oxide–semiconductor devices were fabricated. This article describes the SR lithography system including x‐ray masks, the device fabrication processes, and the characteristics of the resulting devices. Excellent overlay accuracy, better than 90 nm (3 σ), was obtained using chromatic bifocus alignment optics in most levels. Though no radiation effect is observed in initial device characteristics, hot‐electron‐induced instability is observed in 2000 mJ/cm2‐irradiated devices. If high‐speed resists with 100–200 mJ/cm2 sensitivity were used, the instability would be reduced to a negligible level.