Keping Wang

An integrated 60GHz low power two-chip wireless system based on IEEE802.11ad standard

This paper presents our developed two-chip wireless communication system adhering to the IEEE 802.11ad standards with a baseband IC (BBIC) integrated with a low power 60 GHz transceiver SOC (RFIC) and antennas. The novel low power 60GHz RFIC using a sub-harmonic sliding-IF scheme is fully integrated based on low cost SiGe 0.18 um BiCMOS process. The BBIC uses an adaptive time domain equalizer rather than the commonly used frequency domain equalizer to lower the requirements on power consumption.

A low voltage low power highly linear CMOS quadrature mixer using transconductance cancellation technique

This paper presents a low voltage low power high linearity quadrature mixer for software defined radio applications in a 90nm CMOS technology. A 7-dB improvement of input-referred 3^rd-order intermodulation point (IIP<inf>3</inf>) is achieved by using a differential g<inf>m</inf>″ (the second derivation of transconductance) canceling technology. The negative value of g<inf>m</inf>″ in saturated pseudo differential transistor (PDT) is compensated by the positive value of PDT in subthreshold region. The even-order distortion is eliminated by differential PDTs. The mixer consumes a dc power of only 3.8mW under 1V supply. The conversion gain with 10 samples is 3.6∼7.2 dB in the frequency range of 0.3∼6 GHz. the IIP<inf>3</inf> is 7.9∼12.3 dBm 0.3∼6 GHz, whereas the single-sideband noise figure (SSB NF) is 11.1∼14.7 dB.

An inductorless and capacitorless LNA with noise and distortion cancelation

In this paper, a broadband CMOS differential LNA for DC∼2 GHz software defined radio is proposed. The channel thermal noise and the flicker noise of input MOSFET is canceled by exploiting a noise-canceling technique. A lower noise figure and an excellent wide-band input matching can be achieved at the same time. Moreover, the distortions introduced by input MOSFET can be partly cancelled using the proposed technique. The input matching stage and the noise-canceling stage are coupled by a diode. The circuit is fabricated in a 0.18 µm CMOS process. The measurement results show that in DC∼2 GHz, S11 is lower than −11 dB, the gain is between 8∼12 dB, the minimum NF is 3.0 dB, and the OIP3 is >10.4 dBm. It consumes 10 mA under a 1.8V supply. This chip occupies 310 µm × 110 µm core area without any inductors and capacitors.

A Low-Loss Image-Reject Mixer Using Source Follower Isolation Method for DRM/DAB Tuner Applications

A novel low-loss image-reject mixer (IRM) using the source follower isolation method for digital radio mondiale/digital audio broadcasting applications is presented. It is based on double-quadrature mixers (DQMs) and passive polyphase filters (PPFs). The DQM is designed with four passive CMOS mixers. A source follower is inserted between the RF PPF and DQM to decrease the conversion loss of the IRM. Compared with the traditional isolation method, the source follower isolation method shows much higher on-resistance while looking into the RF port of the mixer; meanwhile, the chip area will be greatly decreased. This chip is fabricated in a 0.18-μm CMOS technology. The total conversion loss is 10.5 dB, and the conversion loss per stage of PPFs is 2.1 dB on average. The image-reject ratio is larger than 40 dB in the bandwidth of 1.536 MHz without trimming and calibration. The PldB gain compression point is 7.6 dBm. The chip core area is 1.1 × 1.3 mm2.

A high speed low power pulse swallow frequency divider for DRM/DAB frequency synthesizer

The implementation of a high-speed low-power pulse swallow frequency divider for a DRM/DAB frequency synthesizer, using a 0.18-μm CMOS technology, is described. The frequency divider employs a divide-by-32/33 dual-modulus prescaler, a five bits swallow counter, an 11 bits programmable counter, and a control circuit necessary for the time sequence and operation of the division. In the pulse swallow frequency divider, the divide-by-32/33 dual-modulus prescaler consists of a divider-by-4/5 and an asynchronous divider-by-8 frequency divider, the swallow counter and the programmable counter consist of static-logic fall edge-triggered DFFs. The structure is designed to reduce the power consumption. Post-simulated results show that the programmable dividers operation frequency is from 0.5 GHz to 3.5 GHz with a maximum power consumption of 3.01 mW at 1.8V power supply. The dimension of pulse swallow frequency divider is 270 μm×110 μm.

A CMOS Low-power Temperature-robust RSSI using Weak-inversion Limiting Amplifiers

This paper presents a low-power CMOS receiving signal strength indicator (RSSI). The main architecture of the circuit adopts a six-stage limiting amplifier (LA) in a logarithmic-linear form, which ...

RF front-end ICs for digital radio broadcasting DRM and DAB

A CMOS RF receiver for digital radio broadcasting DRM and DAB applications is presented that contains an RF front-end, an analog baseband, a frequency synthesizer, and a controlling logic unit. In the RF front-end, the noise figure (NF) is minimized by a noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The analog baseband consists of an image-rejection mixer, a 5th-order OTA-C bandpass filter (BPF), two IF VGAs, and a received signal strength indicator (RSSI). The frequency synthesizer is an integer-N PLL based on multi-modulus dividers (MMD), which achieves a wide frequency covering. The circuit is fabricated in a 0.18-µm CMOS technology. The DSB-NF of the RF front-end is 3.1∼6.1 dB while the IIP3 is −4.7∼0.2 dB, and the gain dynamic range is ≫85 dB. The image-rejection radio (IRR) of the image-rejection mixer is ≫40 dB for DAB and ≫45 dB for DRM. The LO phase noise is −69.81 dBc/Hz@10kHz and −108.30 dBc/Hz@1MHz. The chip area is 2.66mm×2.22mm, while drawing a current of 52 mA from a 1.8 V voltage supply.

Embedded Transformed Radial Stub Cell for BPF With Spurious-Free Above Ten Octaves

An embedding cell approach for design of a filter with ultrawide-band rejection and compact size is introduced and investigated. A bandpass filter (BPF) topology design based on the transformed radial stub (TRS) cell embedded resonator (CER) is proposed for the high-performance filter design. The implemented 1.7-GHz BPF with a fractional bandwidth of 1.2% using the TRS CER demonstrates more than 45 dB rejection up to 10.8f0 i.e., 18 GHz. The implemented 1.9-GHz BPF with fractional bandwidth 21% demonstrates 40-dB rejection from 4 to 19 GHz (10f0). The measured passband insertion loss is 2.7 dB, and group delay is around 2.5 nS. The size of the 1.9-GHz fourth-order filter is only 0.408g×0.33 λg, (λg is the guide wavelength at center cutoff frequency) without using any lumped elements.

Radial loaded transformed radial stub for LPF stopband extension

A low pass fllter with ultra-wide band rejection and compact size using a proposed radial loaded transformed radial stubs is introduced and investigated. The implemented unite cell low pass fllter with 1-dB cutofi frequency fc of 3.2GHz demonstrates stopband rejection up to 11.8 fc, i.e., 38GHz. The design is further extended to the high-order LPF through cell cascading. The implemented four-cell LPF with fc of 3.6GHz demonstrated 35dB rejection from 4.8GHz to 39GHz, 50dB rejection from 5.4GHz to 26GHz (7.2 fc) and 20dB rejection from 4.4GHz to 50GHz (13.8 fc). The measured passband insertion loss is less than 1.7dB, and group delay is 0:45 » 0:8nS. The size of the four-cell low pass fllter is only 0:33‚g £ 0:135‚g, (‚g is the guide wavelength at center cutofi frequency) without using any lumped elements.

High Speed Wideband Low Phase Noise 2:1 Frequency Divider

the paper presents the design of a high-speed wideband low phase noise 2:1 frequency divider. A new differential D-latch topology for the divider is presented. Theoretical analysis and an optimization process for the design are given and various phenomena that dominate the speed, the bandwidth and the phase noise behavior of the frequency dividers are discussed. The simulation results show that the frequency divider has an input frequency range from 36 GHz to 6 GHz with a phase noise level of 137.7 dBc/Hz at an offset of 1 MHz, a core power of 12.58 mW and the core area of 70µm×105µm in a 90-nm CMOS process.