Kok Meng Lim

A novel RFCMOS process monitoring test structure

A novel RFCMOS process monitoring test structure has been proposed for the first time in this paper. Excellent agreement in DC and RF characteristics has been observed between conventional test structures and the new process monitoring test structure for both n and p MOSFETs of different device dimensions. This new layout approach can be extended to other devices such as MIM capacitors, diodes, MOS varactors and interconnects.

Novel RF process monitoring test structure for silicon devices

This paper demonstrates a novel RFCMOS process monitoring test structure. Outstanding agreement in dc and radio frequency (RF) characteristics has been observed between conventional test structure and the new process monitoring test structure for MOSFET with good correlations in measured capacitances also noted for metal-insulator-metal capacitor and MOS varactor. Possible process monitoring test structure is also suggested as a reference benchmarking indicator for interconnects.

A CMOS low-power receiving signal strength indicator using weak-inversion limiting amplifiers

Receiving signal strength indicator (RSSI) has been widely used in wireless receiver communication systems such as wireless local personal networks (e.g. Bluetooth), wireless local area networks (e.g. WLAN 802.11a, b, g, j, n), cellular networks (e.g. GSM, UMTS), digital broadcasting (e.g. DAB, DVB-TH), and positioning systems (e.g. GPS) [1–3]. The RSSI is normally employed to represent the received signal power strength. It can also be used to adjust the gains of the RF front-end, analog baseband, and power down the receiver when there is no signal.

A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS process

This paper presents a low power double-quadrature down-conversion mixer for second stage down-conversion application in the 60 GHz receiver chain. The mixer utilizes double-balanced Gilbert-cell topology, and operates over a wide RF bandwidth of 7 GHz centered at 15 GHz, with a LO bandwidth of 4 GHz centered at 12.5 GHz. With low LO drive power requirement of −8dBm, the mixer realizes a conversion gain of 2 dB with a 1 dB flatness across an IF bandwidth of 2.9 GHz. It also has good spurious rejection of more than 40 dBc. The mixer consumes 7.11 mA from a 1.8 V supply, and is fabricated using Tower Jazzs 0.18 μm SiGe BiCMOS process.

Ultra low power active 60 GHz Bi-CMOS down-conversion mixer

A active sub-harmonic mixer is designed for 60 GHz unlicensed-band applications and is fabricated on Jazzs SiGe 0.18 μm high performance process. The mixer has a RF bandwidth of 9 GHz centered at 60 GHz, a LO of 24 GHz of 3.5 GHz bandwidth, with an IF output frequency of 12 GHz. The mixer is able to achieve 4.9 dB of conversion gain including buffer loss. It has an input referred P1dB of −7.6 dBm while achieving extremely low LO drive requirements of −14 dBm. Spurious rejection is better than 30 dBc with reference to IF frequency. Including both RF and DC probe pads it occupies a silicon area of 860 μm × 820 μm. It dissipates only 3.18 mA with a buffer consuming 9.4 mA of current from a 1.8 V voltage supply.

Low power millimeter wave active sige sub-harmonic up-conversion mixer with ultra low driving power

This paper presents a low power sub-harmonic up-convert mixer for 60 GHz unlicensed-band applications and is fabricated using Jazzs SiGe 0.18 µm high frequency process. The mixer operates with a RF bandwidth of 9 GHz centered at 60 GHz, a LO at 24 GHz and has a wideband of 3.5 GHz around an IF frequency of 12 GHz. It is able to achieve −0.1 dB of conversion gain with a differential common emitter buffer. The mixer is able to meet the high linearity specifications with an input referred P1dB of −12.3 dBm while achieving extremely low LO drive requirements of −14 dBm. The up-conversion mixer is able to achieve a spurious rejection better than 20 dBc with reference to RF frequency. It occupies a silicon area of 880 um × 780 um including both RF and DC probe pads. Mixer core dissipates only 1.7 mA of current from a 1.8 V voltage supply.

A 60GHz power amplifier with 12.1 dBm & P1dBCP in 0.18um SiGe BiCMOS process

This paper describes the design and analysis of a four-stages 60GHz SiGe BiCMOS power amplifier. The proposed circuit uses single-ended common-emitter topology that draws 72mW from 1.8V supply. It is able to deliver 12.1dBm output, 17.4dB power gain with a peak 14.1% PAE at its compression point. The S21 has a 3dB bandwidth from 55GHz to 67GHz, which covers the whole of 60GHz band. The power amplifier occupy a silicon area of 1.1 × 0.46 um2 and the measured results show that it can be fully adopted in the 60GHz ISM band applications.

A fully integrated 0.18 µm SiGe BiCMOS low power 60 GHz receiver & transmitter for high data rate wireless communications

In this paper, a 60 GHz low power RX and TX front ends are presented. The RX has more than 19 dB of gain between 58.2 and 67.8 GHz, an average NF of 8.7 across the frequency band of interest, and a P1dB of •24.4 dBm. The high performance RX chip only consumes 32.6 mW of power, including the buffers used to drive measurement equipment. The TX employs the sliding-IF scheme with first IF at one fifth of RF frequency. Results show a saturated power output of 12.7 dBm and a P1dB point at 11 dBm. It provides a bandwidth spanning from 48 GHz to 66 GHz.

A 10GHz 2.8dB gain passive mixer in 0.18um CMOS technology

In this paper, a 10GHz high conversion gain (normally passive mixer is loss) passive mixer is proposed. By proper sizing of LO switches and matching network, the mixer is implemented in standard 0.18 µm CMOS technology. The mixer down-converts a 10 GHz RF frequency to an IF frequency of 1 GHz. An LO power of 0dBm is required to obtain a maximum conversion gain of 2.8dB. It is therefore possible to use the proposed mixer in a receiver without a LNA, a popular architecture in todays ultra low power communication systems.