Jiangmin Gu

An area efficient 64-bit square root carry-select adder for low power applications

The carry-select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However, the conventional carry-select adder (CSL) is still area-consuming due to the dual ripple-carry adder structure. The excessive area overhead makes CSL relatively unattractive but this has been circumvented by the use of an add-one circuit introduced recently. In this paper, an area efficient square root CSL scheme based on a new first zero detection logic is proposed. The proposed CSL witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique. For 64-bit addition, our proposed CSL requires 44% fewer transistors than the conventional one. Simulation results indicate that our proposed CSL can complete 64-bit addition in 1.50 ns and dissipate only 0.35 mW at 1.8V in TSMC 0.18 /spl mu/m CMOS technology.

A novel hybrid pass logic with static CMOS output drive full-adder cell

A novel design of a 1-bit full adder cell featuring a hybrid CMOS logic style is proposed. The simultaneous generation of XOR and XNOR outputs by pass logic is advantageously exploited in a novel complementary CMOS stage to produce full-swing and balanced outputs so that adder cells can be cascaded without buffer insertion. The increase in transistor count of the complementary CMOS stage is compensated by its reduction in layout complexity. Comparing with other 1-bit adder cells using different but uniform logic styles, simulation results show that it is very power efficient and has lower power-delay product over a wide range of voltages.

Ultra low voltage, low power 4-2 compressor for high speed multiplications

This paper presents a new low power 4-2 compressor capable of operating at an ultra-low voltage. Its merits are derived from a novel design of low-power XOR-XNOR gate at transistor level. The new circuit structure eliminates the weak logic on internal nodes in the XOR-XNOR module in contrast to the published designs. Driving capability has been considered in the design so that the 4-2 compressor cells can be used in the tree structured fast multiplier at low supply voltage. Simulation results show that the proposed 4-2 compressor is able to function at supply voltage as low as 0.6 V, and outperforms the conventional CMOS 4-2 compressor and variants of 4-2 compressor constructed with various combinations of recently reported superior low-power logic cells.

Low voltage, low power (5:2) compressor cell for fast arithmetic circuits

This paper presents a new (5:2) compressor circuit capable of operating at ultra-low voltages. Its power efficacy is derived from the novel design of composite XOR-XNOR gate at transistor level. The new circuit eliminates the weak logic and threshold voltage drop problems, which are the main factors limiting the performance of pass transistor based circuits at low supply voltages. The proposed (5:2) compressor has been designed with special consideration on output drivability to ensure that it can function reliably at low voltages when these cells are employed in the tree structured multiplier and multiply-accumulator. Simulation results show that the proposed (5:2) compressor is able to function at supply voltage as low as 0.7 V, and. outperforms other (5:2) compressors constructed with various combinations of recently reported superior low-power logic cells.

A novel low power low voltage full adder cell

The power-delay product is a direct measurement of the energy expended per operational cycle of an arithmetic circuit. Lowering the supply voltage of the full adder cell to achieve low power-delay product is a sensible approach to dramatically improve the power efficiency at sustainable speed of arithmetic circuits composed of such instances at high level design. In this paper, a novel design of a low power 1-bit full adder cell is proposed where the simultaneous generation of XOR and XNOR outputs by pass logic is exploited but with swing restoration circuit added to make ultra low voltage operation down to 0.5 V feasible. A novel complementary CMOS carry generation circuit is devised to produce full-swing and balanced outputs with strong drivability. Simulation results show that our full adder circuit outstrips many latest designs in energy efficiency and has the lowest power-delay product over a wide range of voltages among several low power adder cells of different CMOS logic styles.

Low Power Transmitter Design for BAN

This paper presents a low power, low cost, high integrated transmitter front-end designed for the body area network sensor nodes working at the 2.4 GHz Industry-Science- Medical (ISM) band. Baseband LPF, quadrature up-mixer, differential driver amplifier and T/R switch are designed and implemented in 0.18mum RF CMOS technology. The RC networks based single amplifying block style LPF, modified active up- mixer and two-stage driver amplifier are adopted for large signal processing and low signal distortion. The transmitter outputs OdBm power, with 16dB gain and 8.5dBm 0-IP3, consuming 6mA from 1.8V power supply.

A novel covalent redundant binary Booth encoder

The benefit of high radix Booth encoders in reducing the number of partial products in fast multipliers has been hampered by the complexity of generating the hard multiples. The use of redundant binary (RB) Booth encoder can overcome this problem and avoid the error compensation vector but at the cost of doubling the number of RB partial products. This paper presents a novel covalent RB Booth encoder to generate a compound RB partial product from two adjacent Booth encoded digits. The new encoder fully exploits the characteristics of Booth encoded numbers to restore the effective partial product reduction rate of RB Booth encoder while maintaining the simplicity of hard multiple generators and eliminating the constant correction vector. A legitimate comparison on an 8/spl times/8-bit RB multiplier prototype shows that the multiplier constructed with our proposed Booth encoder consumes lower power and computes faster than those with the normal binary and redundant binary Booth encoders.

High Self-Resonant and Area Efficient Monolithic Transformer Using Novel Intercoil-Crossing Structure for Silicon RFIC

Novel on-chip multiport symmetrical transformer that has high self-resonant frequency and good area efficiency is presented. This technique involves the unique way of intercrossing the transformers primary and secondary coil using multiple metallization layers. A stacked transformer, with the same area utilization as the proposed device, is selected for performance comparison. The proposed design has demonstrated a higher self-resonant frequency in differential transmission line transformer configuration, i.e., f d - SRF(Stacked) = 8 GHz and f d - SRF(Sym) = 10.35 GHz. The structure presented is fully compatible with standard CMOS foundry processes. The silicon data reported in this letter are based on Chartered Semiconductor Manufacturings 0.13-mum RFCMOS technology node.

A CMOS low-power receiving signal strength indicator using weak-inversion limiting amplifiers

Receiving signal strength indicator (RSSI) has been widely used in wireless receiver communication systems such as wireless local personal networks (e.g. Bluetooth), wireless local area networks (e.g. WLAN 802.11a, b, g, j, n), cellular networks (e.g. GSM, UMTS), digital broadcasting (e.g. DAB, DVB-TH), and positioning systems (e.g. GPS) [1–3]. The RSSI is normally employed to represent the received signal power strength. It can also be used to adjust the gains of the RF front-end, analog baseband, and power down the receiver when there is no signal.

A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS process

This paper presents a low power double-quadrature down-conversion mixer for second stage down-conversion application in the 60 GHz receiver chain. The mixer utilizes double-balanced Gilbert-cell topology, and operates over a wide RF bandwidth of 7 GHz centered at 15 GHz, with a LO bandwidth of 4 GHz centered at 12.5 GHz. With low LO drive power requirement of −8dBm, the mixer realizes a conversion gain of 2 dB with a 1 dB flatness across an IF bandwidth of 2.9 GHz. It also has good spurious rejection of more than 40 dBc. The mixer consumes 7.11 mA from a 1.8 V supply, and is fabricated using Tower Jazzs 0.18 μm SiGe BiCMOS process.