Jinna Yan

An integrated 60GHz low power two-chip wireless system based on IEEE802.11ad standard

This paper presents our developed two-chip wireless communication system adhering to the IEEE 802.11ad standards with a baseband IC (BBIC) integrated with a low power 60 GHz transceiver SOC (RFIC) and antennas. The novel low power 60GHz RFIC using a sub-harmonic sliding-IF scheme is fully integrated based on low cost SiGe 0.18 um BiCMOS process. The BBIC uses an adaptive time domain equalizer rather than the commonly used frequency domain equalizer to lower the requirements on power consumption.

A miniaturized 28mW 60GHz differential quadrature sub-harmonic QPSK modulator in 0.18um SiGe BiCMOS

A new sub-harmonic QPSK architecture is proposed for microwave and millimeter-wave applications including transceiver. The developed 60GHz differential quadrature sub-harmonic QPSK modulator based on the proposed new QPSK architecture can not only reject both the image frequency and LO leakages but also reduce the LO operation frequency to the half of the conventional modulator. Moreover, the proposed QPSK modulator provide flexibility to select either the low sideband (LSB) or upper side band (USB) and support data rate as high as 3.52Gbps. The compact chip size is only 400um×300um and power consumption of 28mW is much smaller as compared to that of the state of the arts.

A fully symmetrical 60GHz transceiver architecture for IEEE 802.15.3c application

This paper presents a new multi-conversion super heterodyne architecture for 60GHz broadband wireless application. The proposed design consists of a three-stage conversion with the help of a 24GHz VCO and a divider. The local oscillator frequency stands far away from RF and both IF signals reduce inter-modulate interference. The first and second mixers sharing the same 24GHz VCO relax the complexity and lowering power consumption of both VCO and PLL. Reusing of LO signal without frequency doublers or triplers for multiple conversions reduces power, area and improves efficiency. The topology is symmetrical about the transmitter and receiver sections. This unique feature reduces any circuit mismatches and provides a balance load for the VCO. The proposed design is simulated with ADS at the system level. The transceiver shows high sensitivity and indicates low power design on chip.

A CMOS low-power receiving signal strength indicator using weak-inversion limiting amplifiers

Receiving signal strength indicator (RSSI) has been widely used in wireless receiver communication systems such as wireless local personal networks (e.g. Bluetooth), wireless local area networks (e.g. WLAN 802.11a, b, g, j, n), cellular networks (e.g. GSM, UMTS), digital broadcasting (e.g. DAB, DVB-TH), and positioning systems (e.g. GPS) [1–3]. The RSSI is normally employed to represent the received signal power strength. It can also be used to adjust the gains of the RF front-end, analog baseband, and power down the receiver when there is no signal.

A fully integrated 60GHz dual-chip wireless solution for IEEE802.11ad applications (Invited)

This paper presents our developed dual-chip wireless communication solution adhering to the IEEE 802.11ad standards. The solution is based on a fully integrated baseband IC (BBIC) embedded with USB3.0 interfaces and a low power 60 GHz transceiver SOC (RFIC) embedded inside an antenna in packaging system. The BBIC uses frequency domain equalizer and preambles to perform synchronization, automatic gain control, estimation and compensation for better system performance. A low power 60GHz RFIC using a sub-harmonic sliding-IF scheme is fully integrated based on low cost SiGe 0.18 um BiCMOS process.

A 60GHz BiCMOS self-demodulator with injection locked oscillator

This paper proposes a wide-band self-demodulating receiver for 60GHz ISM band applications. The proposed receiver architecture self-demodulates the OOK input signal by using injection locked oscillator and passive mixer. This simple architecture features extremely ultra-lower-power consumption and faster settling time. Implemented in Tower Jazz 180nm SiGe technology with 200GHz fT, the proposed receiver is able to work at the 60GHz ISM-band frequency range with an OOK data rate up to 2Gbps. The current consumption of the whole receiver is less than 15mA from a single 1.8V supply.

A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS process

This paper presents a low power double-quadrature down-conversion mixer for second stage down-conversion application in the 60 GHz receiver chain. The mixer utilizes double-balanced Gilbert-cell topology, and operates over a wide RF bandwidth of 7 GHz centered at 15 GHz, with a LO bandwidth of 4 GHz centered at 12.5 GHz. With low LO drive power requirement of −8dBm, the mixer realizes a conversion gain of 2 dB with a 1 dB flatness across an IF bandwidth of 2.9 GHz. It also has good spurious rejection of more than 40 dBc. The mixer consumes 7.11 mA from a 1.8 V supply, and is fabricated using Tower Jazzs 0.18 μm SiGe BiCMOS process.

Ultra low power active 60 GHz Bi-CMOS down-conversion mixer

A active sub-harmonic mixer is designed for 60 GHz unlicensed-band applications and is fabricated on Jazzs SiGe 0.18 μm high performance process. The mixer has a RF bandwidth of 9 GHz centered at 60 GHz, a LO of 24 GHz of 3.5 GHz bandwidth, with an IF output frequency of 12 GHz. The mixer is able to achieve 4.9 dB of conversion gain including buffer loss. It has an input referred P1dB of −7.6 dBm while achieving extremely low LO drive requirements of −14 dBm. Spurious rejection is better than 30 dBc with reference to IF frequency. Including both RF and DC probe pads it occupies a silicon area of 860 μm × 820 μm. It dissipates only 3.18 mA with a buffer consuming 9.4 mA of current from a 1.8 V voltage supply.

Low power millimeter wave active sige sub-harmonic up-conversion mixer with ultra low driving power

This paper presents a low power sub-harmonic up-convert mixer for 60 GHz unlicensed-band applications and is fabricated using Jazzs SiGe 0.18 µm high frequency process. The mixer operates with a RF bandwidth of 9 GHz centered at 60 GHz, a LO at 24 GHz and has a wideband of 3.5 GHz around an IF frequency of 12 GHz. It is able to achieve −0.1 dB of conversion gain with a differential common emitter buffer. The mixer is able to meet the high linearity specifications with an input referred P1dB of −12.3 dBm while achieving extremely low LO drive requirements of −14 dBm. The up-conversion mixer is able to achieve a spurious rejection better than 20 dBc with reference to RF frequency. It occupies a silicon area of 880 um × 780 um including both RF and DC probe pads. Mixer core dissipates only 1.7 mA of current from a 1.8 V voltage supply.

A New 24/36-GHz Transceiver architecture for 60-GHz applications

This paper presents a novel 24/36-GHz double conversion heterodyne architecture for IEEE 802.15.3c (60-GHz) applications. The selection of the first local oscillator frequency as 36-GHz gives rise to an intermediate frequency that yields significant cost advantage by reusing the 24-GHz architecture adopted by the automotive industry for both the receiver and transmitter second stage frequency translation. The topology is symmetrical about the transmitter and receiver sections thus taking care of mismatch issues at the circuit level implementation. The system level simulation shows high image rejection ratio and low requirement on image rejection low noise amplifier (LNA) and mixer design. The proposed architecture reduces the influence of harmonics and sub-harmonics during the mixer phase and exhibits less inter-modulation interference.