Kerry Veenstra

A dual granularity and globally interconnected architecture for a programmable logic device

A novel architecture called FLEX (flexible logic element matrix) has been designed which supports high logic densities up to 24,000 gates, maximizing overall system performance in a user design. This has been accomplished through a dual granularity approach and a global interconnect strategy. The dual granularity and global interconnect approach has succeeded in supporting both short nets and long nets for maximum performance.

A machine learning framework for TCP round-trip time estimation

In this paper, we explore a novel approach to end-to-end round-trip time (RTT) estimation using a machine-learning technique known as the experts framework. In our proposal, each of several ‘experts’ guesses a fixed value. The weighted average of these guesses estimates the RTT, with the weights updated after every RTT measurement based on the difference between the estimated and actual RTT.Through extensive simulations, we show that the proposed machine-learning algorithm adapts very quickly to changes in the RTT. Our results show a considerable reduction in the number of retransmitted packets and an increase in goodput, especially in more heavily congested scenarios. We corroborate our results through ‘live’ experiments using an implementation of the proposed algorithm in the Linux kernel. These experiments confirm the higher RTT estimation accuracy of the machine learning approach which yields over 40% improvement when compared against both standard transmission control protocol (TCP) as well as the well known Eifel RTT estimator. To the best of our knowledge, our work is the first attempt to use on-line learning algorithms to predict network performance and, given the promising results reported here, creates the opportunity of applying on-line learning to estimate other important network variables.

Programmable memory blocks supporting content-addressable memory

The Embedded System Block (ESB) of the APEX E programmable logic device family from Altera Corporation includes the capability of implementing content addressable memory (CAM) as well as product term macrocells, ROM, and dual port RAM. In CAM mode each ESB can implement a 32 word CAM with 32 bits per word. In product term mode, each ESB has 16 macrocells built out of 32 product terms with 32 literal inputs. The ability to reconfigure memory blocks in this way represents a new and innovative use of resources in a programmable logic device, requiring creative solutions in both the hardware and software domains. The architecture and features of this Embedded System Block are described.

Optimizations for a highly cost-efficient programmable logic architecture

Architects of programmable logic devices (PLDs) face several challenges when optimizing a new device family for low manufacturing cost. When given an aggressive die-size goal, functional blocks that seem otherwise insignificant become targets for area reduction. Once low die cost is achieved, it is seen that testing and packaging costs must be considered. Interactions among these three cost contributors pose trade-offs that prevent independent optimization. This paper discusses solutions discovered by the architects optimizing the Altera FLEX 6000 architecture.

Guiding sensor-node deployment over 2.5D terrain

We propose a novel distributed deployment algorithm for sensor networks whose nodes reside upon and are obstructed by 2.5D terrain. Our algorithm optimizes area coverage by computing cumulative visibility over terrain. Through simulation and comparison to centralized algorithms, we demonstrate that our distributed algorithm achieves good results and degrades gracefully with reduced internode communication. To the best of our knowledge, our distributed deployment algorithm is the first use of a distributed simulated annealing algorithm for sensor network deployment. In addition, to our knowledge, this is the first time range-limited cumulative visibility is used to guide sensor deployment over 2.5D terrain. Our results show that a centralized Simulated Annealing algorithm outperforms Pattern Search and Gradient Ascent approaches. Results also show that our version of Distributed Simulated Annealing performs well, degrading gracefully as communication radius is reduced.

TerrainLOS: An Outdoor Propagation Model for Realistic Sensor Network Simulation

We present TerrainLOS, an outdoor propagation model that uses Digital Elevation Models to determine whether two nodes can communicate. We have implemented TerrainLOS in the sensor network simulator COOJA and used it to evaluate how the roughness of terrain, which we classify using Average Cumulative Visibility, affects the number of edges, connectedness, latency, and power of a network. We compare the difference in results when using TerrainLOS and a simpler propagation model to show how the performance of outdoor simulation is greatly affected by a model that takes terrain into account.

A silicon efficient FLEX 6000 programmable logic architecture

An SRAM based PLD architecture ranging from 5000 to 24000 gates has been developed. The primary focus of the architecture is on low cost, high performance, and routability. Breakthroughs in interconnect scheme have been made to achieve flexible routing and high cost efficiency in the interconnect, logic array blocks, and I/O elements. Other architecture features include built-in low skew clock, programmable output slew rate control, PCI compliant I/O, JTAG boundary scan, individual output enable for each I/O pin, and in-circuit configuration. The first member of the family is currently available with 16000 gate density and 125 MHz performance for 16-bit counter application.