Kevin Chuang

60GHz single-chip CMOS digital radios and phased array solutions for gaming and connectivity

In this paper, we present four examples of highly integrated 60 GHz single-chip CMOS 90 nm digital radios and phased array solutions. These solutions include for the first time digital-to-analog/analog-to-digital conversion and embedded multi-gigabit mixed signal modem requiring no external processing. This convergence of 60 GHz CMOS digital radio, low power multi-gigabit mixed-signal processing and digital signal processing on a single chip offers the lowest energy per bit transmitted wirelessly at multi-gigabit rate to meet the very stringent low-power specifications for battery operated consumer electronic portable devices. Layout and temperature dependent 60 GHz CMOS 90 nm model development and critical high performance analog and mixed building blocks are presented as fundamental enablers for single chip integration. The designs have been optimized for robustness against process variation and temperature, and verified by measurement results.

60GHz CMOS/PCB co-design and phased array technology

In this paper, we present a highly integrated 60 GHz CMOS/PCB single-chip digital phased array solution, embedded in QFN package. This represents a unique opportunity to develop low power 60GHz multi-gigabit radio at a similar cost structure as a Bleutooth® radio, addressing the needs of a multitude of bandwidth hungry wireless multimedia applications such as high definition streaming and massive side-loading. The convergence of 60GHz CMOS digital radio, phased array technology, low power multi-gigabit mixed-signal processing low cost filter, phased array antenna embedded in standard package is discussed. In addition, uncompressed HDMI video streaming is demonstrated for the first time, using a standard battery (AAA) operated compact 60GHz CMOS/PCB QFN based module. These solutions offer the lowest energy per bit transmitted wirelessly at multi-gigabit rate, reported till date, to meet the very stringent low-power specifications for battery operated consumer electronic portable devices.

An adaptive broadband BiCMOS active spur canceller

An active interference cancellation system is presented in BiCMOS 8HP capable of eliminating undesired signals resulting from an on-chip clock whose fundamental and/or harmonics couple into a receiver path. The cancellation system is capable of eliminating undesired clock fundamentals from 6 – 10 GHz and its harmonics up to 30 GHz. By modeling the coupling channel, the system recovers receiver sensitivity and is independent of the aggressing clock rate and amplitude fluctuations. A variable phase rotator, comb generator, and an amplitude modulator are used to achieve the cancellation. The use of a comb generator in a cancellation system is novel and enables harmonic cancellation. Over 25 dB of cancellation for an aggressing clock and its harmonics have been achieved. A series-to-parallel bus that communicates with all system sub-blocks provides a healing aspect to the system. The total power consumption of the canceller system is 71 mW.

On the development of CMOS mmW and sub-THz phased array technology for communication/sensing nodes

In this paper, we present a single chip cross-layer approach for a new class of highly integrated CMOS millimeter wave and sub-THz communication and sensing wireless systems. It is based on the convergence of fully integrated CMOS digital radio and beam former, low power multi-gigabit mixed-signal processing and low cost packaging with embedded antenna. A 60GHz CMOS/PCB portable beam-former solution and highly scalable V-band CMOS 45nm architecture are highlighted as leading edge examples of such an approach, enabling breakthrough power/size reduction as well as multi-gigahertz bandwidth and processing speeds. These single chip millimeter wave and sub-THz system-on-chip solutions are the fundamental enablers for a wide range of communication and sensing applications operating from V-band to W-band and beyond.