Kevin L. Lin

Scaling Limits of Electrostatic Nanorelays

A model to explore the scaling limits of electrostatically actuated nanorelays is presented, which shows that adhesion in a nanorelays contact interface limits its performance with respect to operating voltage, contact resistance, and switching energy. For logic applications, we show that an ultimately scaled relay can be more efficient than conventional metal-oxide-semiconductor devices if (1) it is designed with very high contact resistances, leading to ≈ 1-MHz operation due to large RC delays, or (2) its actuation area is extremely large compared with its contacting area, leading to very low voltage operation, which reduces overall CV2 losses. We propose new relay scaling relations that account for the scaling of contact interfaces.

Adhesion Limits and Design Criteria for Nanorelays

Microelectromechanical switches are of interest for low-power circuit applications due to their minimal OFF state leakage current. This paper uses 22-nm CMOS fabrication technology and the clamped cantilever geometry as the basis for establishing design rules for electrostatic nanorelays and estimates the design parameters needed for nanorelay actuation. The adhesive pull-off force of various substrate/cantilever combinations is simulated using molecular dynamics with a force field that parameterizes van der Waals interactions, and measured using atomic force microscopy. Both methods show that for the substrates studied, H-passivated Si produces the least adhesive surface with adhesive pressure close to the critical pressure required for pull-out. Experimental results quantifying adhesion and electrical current conduction show that it is impossible to simultaneously meet the adhesion and current conduction requirements of a nanorelay. We show that contact adhesion is the key parameter limiting the scalability of electromechanical relays at the nanoscale.

Demonstration of a sidewall capacitor to evaluate dielectrics and metal barrier thin films

A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to those measured on an integrated vehicle. SW CAP results are useful for comparing electrical reliability of different dielectric systems, and effective in determining physical continuity of copper metal barriers.

Demonstration of new planar capacitor (PCAP) vehicles to evaluate dielectrics and metal barrier thin films

Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposing differences between leaky and good etch stop films. Fillable planar capacitors are also fabricated and results presented for that class of fill materials.

Nickel silicide for interconnects

Nickel silicide is an attractive option for interconnects at small dimensions because of its short electron mean free path and good electromigration behavior. Nickel silicide interconnects can be integrated using either a subtractive or damascene process. Precise control of final metal composition ratio is important for obtaining low resistivity, as shown in thin-film and patterned structure measurements.

The effect of device fabrication on quasi-static elastic behaviour of silicon nanocantilever arrays

As CMOS technology scaling continues, leakage current is increasingly degrading energy efficiency. The leakage problem can potentially be addressed by nanoelectromechanical (NEMS) relay technology, where the off state leakage current is virtually zero. These devices incorporate a suspended nanobeam which is drawn across a gap to make contact in similar fashion to a traditional relay. The properties of this nanobeam must be carefully engineered to minimise stiffness (hence operating voltage), while simultaneously maintaining sufficient restoring force to overcome the adhesion forces at the contact surface which are significant at the nanoscale. To engineer the beam stiffness, detailed understanding of the beam composition and geometry, combined with accurate modelling is required. Simple analytical models over-estimate the stiffness of the cantilever beam along its length, and both analytical and FEA models which account for the manufacturing induced geometrical complexity are required. In this work, spatial force mapping of fabricated beams was used to experimentally validate analytical and FEA models incorporating detailed beam dimensions. An excellent fit was achieved, and this provides a method for targeting beam properties in a NEMS device.