Kevin Orvek

Materials issues for optical components and photomasks in 157 nm lithography

Photolithography using 157 nm pulsed fluorine lasers has emerged as the leading candidate technology for the post-193-nm generation. Preliminary data have indicated that at 157 nm there are optical materials transparent enough to enable the fabrication of refractive elements, both in the projection and illumination part of the optical train. However, a number of critical issues still remain. Optical materials must show no appreciable degradation with laser irradiation. The availability of transparent photomask substrates must be ascertained. Optical coatings must be developed and qualified. At this short wavelength, interface effects, subsurface damage, and adsorbate effects become increasingly prominent. We present recent experimental results on the durability tests of calcium fluoride, modified fused silica, and optical coatings for 157 nm applications. Our initial assessment of several grades of modified fused silica demonstrates that at least one grade already meets transparency and durability require...

SEMATECH EUVL mask program status

As we approach the 22nm half-pitch (hp) technology node, the industry is rapidly running out of patterning options. Of the several lithography techniques highlighted in the International Technology Roadmap for Semiconductors (ITRS), the leading contender for the 22nm hp insertion is extreme ultraviolet lithography (EUVL). Despite recent advances with EUV resist and improvements in source power, achieving defect free EUV mask blank and enabling the EUV mask infrastructure still remain critical issues. To meet the desired EUV high volume manufacturing (HVM) insertion target date of 2013, these obstacles must be resolved on a timely bases. Many of the EUV mask related challenges remain in the pre-competitive stage and a collaborative industry based consortia, such as SEMATECH can play an important role to enable the EUVL landscape. SEMATECH based in Albany, NY is an international consortium representing several of the largest manufacturers in the semiconductor market. Full members include Intel, Samsung, AMD, IBM, Panasonic, HP, TI, UMC, CNSE (College of Nanoscience and Engineering), and Fuller Road Management. Within the SEMATECH lithography division a major thrust is centered on enabling the EUVL ecosystem from mask development, EUV resist development and addressing EUV manufacturability concerns. An important area of focus for the SEMATECH mask program has been the Mask Blank Development Center (MBDC). At the MBDC key issues in EUV blank development such as defect reduction and inspection capabilities are actively pursued together with research partners, key suppliers and member companies. In addition the mask program continues a successful track record of working with the mask community to manage and fund critical mask tools programs. This paper will highlight recent status of mask projects and longer term strategic direction at the MBDC. It is important that mask technology be ready to support pilot line development HVM by 2013. In several areas progress has been made but a continued collaborative effort will be needed along with timely infrastructure investments to meet these challenging goals.

Electrostatic chucking for extreme ultraviolet lithography: Simulations and experiments

The purpose of this research is to assess the effectiveness of electrostatic chucks in reducing low-spatial frequency mask (or reticle) flatness variations and to validate finite element (FE) models of the chuck-mask interaction. The flatness of a sample extreme ultraviolet lithography reticle and an electrostatic pin chuck were measured using a Zygo interferometer. The measured flatness data were entered into the FE models, and electrostatic chucking was simulated by applying an area-weighted average pressure on the reticle. The shape of the mask when clamped by the electrostatic chuck was then predicted using the FE model. To validate these predictions, experiments were conducted in which the previously measured reticle was electrostatically clamped using the pin chuck. These experiments were conducted in a vacuum chamber to minimize the effects of humidity. Interferometric plots of the chucked reticle surface were obtained and compared with the FE predictions. It was found that the measured and predict...

Status of EUV reticle handling solution in meeting 32 nm HP EUV lithography

Significant progress has been made over the past several years in developing extreme ultraviolet (EUV) mask infrastructure, especially in EUV reticle handling and protection. Today, the industry has converged to standardize the dual pod reticle carrier approach in developing EUV reticle handling solutions. SEMATECH has already established reticle handling infrastructure compliant with industrys draft standard, including carrier, robotic carrier handling, automated carrier cleaning, vacuum protection, and state-of-the-art particulate contamination testing capabilities. It proves to be one of the key enablers in developing EUV reticle protection solutions, through broad collaboration with industry stakeholders and suppliers. In this paper, we discuss our in-house reticle handling infrastructure and provide insights on how to apply it in EUV lithography pilot line development and future production line. We present particulate contamination free baseline results of state-of-the-art EUV reticle carriers, i.e., sPod, throughout lifecycle uses. We will also compare the results against requirements for 32 nm half-pitch (HP) EUV lithography, to identify the remaining challenges ahead of the industry.

Evaluation of an e-beam correction strategy for compensation of EUVL mask non-flatness

In extreme ultraviolet lithography (EUVL), mask non-flatness contributes to overlay errors in EUVL scanners. Tight non-flatness targets are required to meet future overlay; for example, the International Technology Roadmap for Semiconductors (ITRS) requires that substrate non-flatness will need to decrease to 36 nm peak-to-valley in 2013. To meet these tight non-flatness values, suppliers must use aggressive polishing steps, adversely impacting substrate yield and mask blank cost of ownership. An alternative option is to use image placement corrections at the writing step of the reticle to compensate for the predicted impact of the non-flatness pattern placement errors, which would allow the specifications to be relaxed. In this paper, we will present the results of using e-beam image placement corrections during mask writing to compensate for mask non-flatness. A low thermal expansion material (LTEM) substrate with about 500 nm of nonflatness was employed. Three different compensation methods were used to calculate the predicted image placement errors based upon the mask non-flatness, including the expected errors from scanner chucking. The mask was designed to use a repeating set of four ASML alignment marks (XPA marks) across the mask. During e-beam writin, one mark was left uncompensated, and the three different compensation methods were applied to the remaining marks. The masks were exposed using the ASML alpha demo tool (ADT). An overview of the viability of e-beam correction methodologies to compensate for mask non-flatness is presented based upon the wafer overlay results.

Protection Efficiency of a Standard Compliant EUV Reticle Handling Solution

For successful implementation of extreme ultraviolet lithography (EUVL) technology for late cycle insertion at 32 nm half-pitch (hp) and full introduction for 22 nm hp high volume production, the mask development infrastructure must be in place by 2010. The central element of the mask infrastructure is contamination-free reticle handling and protection. Today, the industry has already developed and balloted an EUV pod standard for shipping, transporting, transferring, and storing EUV masks. We have previously demonstrated that the EUV pod reticle handling method represents the best approach in meeting EUVL high volume production requirements, based on then state-of-the-art inspection capability at ~53nm polystyrene latex (PSL) equivalent sensitivity. In this paper, we will present our latest data to show defect-free reticle handling is achievable down to 40 nm particle sizes, using the same EUV pod carriers as in the previous study and the recently established worlds most advanced defect inspection capability of ~40 nm SiO2 equivalent sensitivity. The EUV pod is a worthy solution to meet EUVL pilot line and pre-production exposure tool development requirements. We will also discuss the technical challenges facing the industry in refining the EUV pod solution to meet 22 nm hp EUVL production requirements and beyond.

Correlation of overlay performance and reticle substrate non-flatness effects in EUV lithography

Image placement (IP) and overlay error specifications in the International Technology Roadmap for Semiconductors (ITRS) continue to get tighter with each successive technology node. One of the significant contributors to IP error is the non-flatness of the reticle substrate. In this paper, we will discuss in detail the effect of reticle substrate shape on the overlay performance in extreme ultraviolet (EUV) tools. Substrate shape-induced overlay effects are important when multiple device levels are printed using EUV lithography. We present an analysis of 20 blanks with different flatness specifications for overlay signatures when used for printing multiple device levels. A comprehensive analysis of scanner correctable and non-correctable errors for different substrate shapes will also be presented. Non-flatness specifications for EUV blanks will be reviewed based on these reticle-matching results. We will discuss results from flatness measurements and the effect on overlay budget due to mismatched substrates using several substrates with different flatness specifications.

Status and path to a final EUVL reticle-handling solution

In extreme ultraviolet lithography (EUVL), the lack of a suitable material to build conventional pellicles calls for industry standardization of new techniques for protection and handling throughout the reticles lifetime. This includes reticle shipping, robotic handling, in-fab transport, storage, and uses in atmospheric environments for metrology and vacuum environments for EUV exposure. In this paper, we review the status of the industry-wide progress in developing EUVL reticle-handling solutions. We show the industrys leading reticle carrier approaches for particle-free protection, such as improvements in conventional single carrier designs and new EUVL-specific carrier concepts, including variations on a removable pellicle. Our test indicates dual pod approach of the removable pellicle led to nearly particle-free use during a simulated life cycle, at ~50nm inspection sensitivity. We will provide an assessment of the remaining technical challenges facing EUVL reticle-handling technology. Finally, we will review the progress of the SEMI EUVL Reticle-handling Task Force in its efforts to standardize a final EUV reticle protection and handling solution.

Electrostatic chucking of EUVL reticles

Characterizing the effect of electrostatic chucking on the flatness of Extreme Ultraviolet Lithography (EUVL) reticles is necessary for the implementation of EUVL for the sub-32 nm node. In this research, finite element (FE) models have been developed to predict the flatness of reticles when clamped by a bipolar Coulombic pin chuck. Nonflatness measurements of the reticle and chuck surfaces were used to create the model geometry. Chucking was then simulated by applying forces consistent with the pin chuck under consideration. The effect of the nonuniformity of electrostatic forces due to the presence of gaps between the chuck and reticle backside surfaces was also included. The model predictions of the final pattern surface shape of the chucked reticle have been verified with chucking experiments and the results have established the validity of the models. Parametric studies with varying reticle shape, chuck shape, chuck geometry, and chucking pressure performed using FE modeling techniques are extremely useful in the development of SEMI standards for EUVL.

SEMATECH mask program

Defect free masks are a critical component to enable extreme ultraviolet lithography (EUVL). It is projected EUVL will be inserted for the 22nm hp node with a timeframe of 2012-2013 for leading IC manufacturers. To meet the goal of defect free masks, a concerted effort is required with emphasis on mask blank development and mask infrastructure readiness. With this in mind, SEMATECH mask program has been uniquely positioned to make important contributions to these areas. Together with several partners, an overall strategy has been defined focused on meeting EUVL mask requirements including setting mask standards and enabling the mask-making infrastructure. This paper will highlight the overview of key projects and accomplishments from the mask blank development program. It is critical that SEMATECH and its partners be ready to meet the overall pilot line defect density requirement of 0.04 defects/cm2 at 18nm defect sensitivity by the end of 2010. Although important progress has been made, much work remains to meet these challenging goals.