Jaewoong Sohn

Resist outgassing contamination growth results using both photon and electron exposures

During exposure in an EUV scanner, photoresist and other materials coated on a wafer are known to outgas various species. As a requirement to pattern materials in an ASML NXE scanner, these materials need to be screened for outgassing and possible optics contamination. As part of the testing process, a resist-coated wafer is exposed in a vacuum chamber mimicking the conditions inside an EUV scanner. The resist exposure source can be either EUV photons or electron beam (e-beam). This presentation will cover the results to date on a SEMATECH program to study resist outgassing from both the commercial system from EUV Tech and a custom Resist Outgassing and Exposure (ROX) tool. The EUV Tech results reported will be based on electron exposures of the photoresist, and the ROX results reported will be based on EUV photon exposures of the photoresist. The results reported will cover both tools and the measurements of over 80 commercial photoresists.

Electrostatic chucking for extreme ultraviolet lithography: Simulations and experiments

The purpose of this research is to assess the effectiveness of electrostatic chucks in reducing low-spatial frequency mask (or reticle) flatness variations and to validate finite element (FE) models of the chuck-mask interaction. The flatness of a sample extreme ultraviolet lithography reticle and an electrostatic pin chuck were measured using a Zygo interferometer. The measured flatness data were entered into the FE models, and electrostatic chucking was simulated by applying an area-weighted average pressure on the reticle. The shape of the mask when clamped by the electrostatic chuck was then predicted using the FE model. To validate these predictions, experiments were conducted in which the previously measured reticle was electrostatically clamped using the pin chuck. These experiments were conducted in a vacuum chamber to minimize the effects of humidity. Interferometric plots of the chucked reticle surface were obtained and compared with the FE predictions. It was found that the measured and predict...

Evaluation of an e-beam correction strategy for compensation of EUVL mask non-flatness

In extreme ultraviolet lithography (EUVL), mask non-flatness contributes to overlay errors in EUVL scanners. Tight non-flatness targets are required to meet future overlay; for example, the International Technology Roadmap for Semiconductors (ITRS) requires that substrate non-flatness will need to decrease to 36 nm peak-to-valley in 2013. To meet these tight non-flatness values, suppliers must use aggressive polishing steps, adversely impacting substrate yield and mask blank cost of ownership. An alternative option is to use image placement corrections at the writing step of the reticle to compensate for the predicted impact of the non-flatness pattern placement errors, which would allow the specifications to be relaxed. In this paper, we will present the results of using e-beam image placement corrections during mask writing to compensate for mask non-flatness. A low thermal expansion material (LTEM) substrate with about 500 nm of nonflatness was employed. Three different compensation methods were used to calculate the predicted image placement errors based upon the mask non-flatness, including the expected errors from scanner chucking. The mask was designed to use a repeating set of four ASML alignment marks (XPA marks) across the mask. During e-beam writin, one mark was left uncompensated, and the three different compensation methods were applied to the remaining marks. The masks were exposed using the ASML alpha demo tool (ADT). An overview of the viability of e-beam correction methodologies to compensate for mask non-flatness is presented based upon the wafer overlay results.

Protection Efficiency of a Standard Compliant EUV Reticle Handling Solution

For successful implementation of extreme ultraviolet lithography (EUVL) technology for late cycle insertion at 32 nm half-pitch (hp) and full introduction for 22 nm hp high volume production, the mask development infrastructure must be in place by 2010. The central element of the mask infrastructure is contamination-free reticle handling and protection. Today, the industry has already developed and balloted an EUV pod standard for shipping, transporting, transferring, and storing EUV masks. We have previously demonstrated that the EUV pod reticle handling method represents the best approach in meeting EUVL high volume production requirements, based on then state-of-the-art inspection capability at ~53nm polystyrene latex (PSL) equivalent sensitivity. In this paper, we will present our latest data to show defect-free reticle handling is achievable down to 40 nm particle sizes, using the same EUV pod carriers as in the previous study and the recently established worlds most advanced defect inspection capability of ~40 nm SiO2 equivalent sensitivity. The EUV pod is a worthy solution to meet EUVL pilot line and pre-production exposure tool development requirements. We will also discuss the technical challenges facing the industry in refining the EUV pod solution to meet 22 nm hp EUVL production requirements and beyond.

A study of reticle non-flatness induced image placement error contributions in EUV lithography

Image placement (IP) and overlay error specifications are serious concerns for lithography at each successive technology node. Some of the primary contributors to image placement error (IPE) in EUV lithography are reticle and chuck surface non-flatness and chucking flatness non- uniformity. Flatness compensation has been proposed as a method to relax flatness specification for EUV substrates. However, in order for flatness compensation to work effectively, the various components of IPE i.e., reticle flattening and as-chucked z-height variation needs to be estimated accurately. Flatness compensation models assume a completely flat, rigid chuck and conformal clamping of the reticle backside. In this paper we will describe experiments designed to verify the different assumptions that the flatness compensation models are based on. The experiments involve printing wafers using a set of reticles of different flatness specifications on the ASML EUV Alpha Demo Tool (ADT) in Albany, NY. We will discuss results from these experiments and use Finite Element Modeling to simulate reticle chucking to correlate these results to physical properties electrostatic chuck on the ADT.

Correlation of overlay performance and reticle substrate non-flatness effects in EUV lithography

Image placement (IP) and overlay error specifications in the International Technology Roadmap for Semiconductors (ITRS) continue to get tighter with each successive technology node. One of the significant contributors to IP error is the non-flatness of the reticle substrate. In this paper, we will discuss in detail the effect of reticle substrate shape on the overlay performance in extreme ultraviolet (EUV) tools. Substrate shape-induced overlay effects are important when multiple device levels are printed using EUV lithography. We present an analysis of 20 blanks with different flatness specifications for overlay signatures when used for printing multiple device levels. A comprehensive analysis of scanner correctable and non-correctable errors for different substrate shapes will also be presented. Non-flatness specifications for EUV blanks will be reviewed based on these reticle-matching results. We will discuss results from flatness measurements and the effect on overlay budget due to mismatched substrates using several substrates with different flatness specifications.

Ion beam deposition system for depositing low defect density extreme ultraviolet mask blanks

Extreme ultraviolet lithography (EUVL) is the leading next-generation lithography (NGL) technology to succeed optical lithography at the 22 nm node and beyond. EUVL requires a low defect density reflective mask blank, which is considered to be one of the top two critical technology gaps for commercialization of the technology. At the SEMATECH Mask Blank Development Center (MBDC), research on defect reduction in EUV mask blanks is being pursued using the Veeco Nexus deposition tool. The defect performance of this tool is one of the factors limiting the availability of defect-free EUVL mask blanks. SEMATECH identified the key components in the ion beam deposition system that is currently impeding the reduction of defect density and the yield of EUV mask blanks. SEMATECHs current research is focused on in-house tool components to reduce their contributions to mask blank defects. SEMATECH is also working closely with the supplier to incorporate this learning into a next-generation deposition tool. This paper will describe requirements for the next-generation tool that are essential to realize low defect density EUV mask blanks. The goal of our work is to enable model-based predictions of defect performance and defect improvement for targeted process improvement and component learning to feed into the new deposition tool design. This paper will also highlight the defect reduction resulting from process improvements and the restrictions inherent in the current tool geometry and components that are an impediment to meeting HVM quality EUV mask blanks will be outlined.

Effect of electrostatic chucking and substrate thickness uniformity on extreme ultraviolet lithography mask flatness

Extreme ultraviolet lithography (EUVL) is one of the leading candidates for next-generation lithography in the sub-45 nm regime. Successful implementation of this technology will depend upon advancements in many areas, including the quality of the mask system to control image placement errors. Such errors will occur at the wafer as a result of height variations of the patterned (frontside) mask surface (i.e., its nonflatness). The Semiconductor Equipment and Materials International EUVL Mask Standard (SEMI P37) specifies that the mask frontside and backside nonflatness be no more than 50 nm peak-to-valley (P-V). Currently, the lowest level of freestanding flatness of EUVL mask substrates from production-level polishing and finishing techniques is about 200 nm P-V. The frontside and backside of typical (and representative) EUVL substrates were measured for flatness and these surfaces were represented mathematically using Legendre polynomials. The Legendre coefficients were then utilized in a finite element...

Resist outgassing contamination on EUV multilayer mirror analogues

EUV lithography is a technology enabling next generation electronic devices, but issues with photoresist sensitivity, resolution and line edge roughness as well as tool downtime and throughput remain. As part of the industrys efforts to address these problems we have worked with resist suppliers to quantify the relative contamination rate of a variety of resists on EUV multilayer mirror analogues following ASML approved protocols. Here we present results of our ongoing program to better understand the effect of process parameters such as dose and resist thickness on the contamination rate of ruthenium coated witness plates, additionally we present results from a study on the effectiveness of hydrogen cleaning.